Operational amplifier design with gain-enhancement differential amplifier

This paper discusses a gain-enhancement differential amplifier circuit with positive feedback. The circuit is designed with short-channel MOSFETs, low power, and low voltage, resulting in DC gain improvement over a conventional complementary-metal-oxide-semiconductor (CMOS) diff-amp and comparable to a known published diff-amp circuit. In addition, noise and distortion analyses are shown on diff-amps. This paper also describes two operational amplifier (op-amp) circuits, which are designed with the new gain-enhancement diff-amp.

[1]  Randall L. Geiger,et al.  Positive feedback gain-enhancement techniques for amplifier design , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[2]  H.L. Hess,et al.  Method to improve total dose radiation hardness in a CMOS dc-dc boost converter , 2005, Twentieth Annual IEEE Applied Power Electronics Conference and Exposition, 2005. APEC 2005..

[3]  J. Burleson,et al.  Maximum intrinsic gain degradation in technology scaling , 2007, 2007 International Semiconductor Device Research Symposium.

[4]  Ramesh Harjani,et al.  Partial positive feedback for gain enhancement of low-power CMOS otas , 1995 .

[5]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[6]  Randall L. Geiger,et al.  A negative conductance voltage gain enhancement technique for low voltage high speed CMOS op amp design , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[7]  Randall L. Geiger,et al.  All digital transistor high gain operational amplifier using positive feedback technique , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[8]  Sergio Franco,et al.  Design with Operational Amplifiers and Analog Integrated Circuits , 1988 .

[9]  Randall L. Geiger,et al.  A high gain strategy with positive-feedback gain enhancement technique , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[11]  W. Sansen Challenges in analog IC design submicron CMOS technologies , 1996, 1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings.

[12]  R. Jacob Baker,et al.  CMOS Circuit Design, Layout, and Simulation , 1997 .

[13]  Bogdan M. Wilamowski,et al.  VLSI implementation of cross-coupled MOS resistor circuits , 2001, IECON'01. 27th Annual Conference of the IEEE Industrial Electronics Society (Cat. No.37243).

[14]  Hossein Shamsi,et al.  A new two-stage Op-Amp using gate-driven, and positive feedback techniques , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.