A Real-Time Virtual Re-Convergence Hardware Platform

In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.

[1]  Chung-Hyun Ahn,et al.  Virtual Control of Optical Axis of the 3DTV Camera for Reducing Visual Fatigue in Stereoscopic 3DTV , 2004 .

[2]  Gauthier Lafruit,et al.  Fast Variable Center-Biased Windowing for High-Speed Stereo on Programmable Graphics Hardware , 2007, 2007 IEEE International Conference on Image Processing.

[3]  Tian-Sheuan Chang,et al.  Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight , 2010, IEEE Transactions on Circuits and Systems for Video Technology.

[4]  I. Ohzawa,et al.  Stereoscopic depth discrimination in the visual cortex: neurons ideally suited as disparity detectors. , 1990, Science.

[5]  John Iselin Woodfill,et al.  Tyzx DeepSea High Speed Stereo Vision System , 2004, 2004 Conference on Computer Vision and Pattern Recognition Workshop.

[6]  Richard Szeliski,et al.  A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms , 2001, International Journal of Computer Vision.

[7]  Peter A. Howarth,et al.  Visual fatigue caused by viewing stereoscopic motion images: Background, theories, and observations , 2008, Displays.

[8]  Sung-Chul Lee,et al.  An Optimized Stacked Driver for Synchronous Buck Converter , 2012 .

[9]  Jun-Dong Cho,et al.  A Real-time Compact Structured-light based Range Sensing System , 2012 .

[10]  Kwanghoon Sohn,et al.  Fast Dense Stereo Matching Using Adaptive Window in Hierarchical Framework , 2006, ISVC.

[11]  Yoonjin Kim.  Reconfigurable Multi-Array Architecture for Low- Power and High-Speed Embedded Systems , 2011 .

[12]  M. Maymandi-Nejad,et al.  A monotonic digitally controlled delay element , 2005, IEEE Journal of Solid-State Circuits.

[13]  A. C. Sonmez,et al.  FPGA design and implementation of a real-time stereo vision system , 2012, 2012 International Symposium on Innovations in Intelligent Systems and Applications.