A new parallel algorithm for CRC generation

Cyclic redundancy check (CRC) is one of the most important error-detection schemes used in digital communications. A new parallel algorithm for CRC generation and its software as well as hardware implementation is described. For the software implementation, this paper has focused on the 32-bit CRC used in the Ethernet, computed on a general purpose PowerPC microprocessor with the new AltiVec technology. A speedup by a factor of 4.57 over the standard table-lookup algorithm was obtained. A hardware implementation of the algorithm is then discussed, which yields an unlimited speed-up potential over the bit-wise serial algorithm.

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