High-Density Through Silicon Vias for 3-D LSIs
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[1] Jun Deguchi,et al. NEUROMORPHIC ANALOG CIRCUITS FOR THREE-DIMENSIONALLY STACKED VISION CHIP , 2006 .
[2] Katsuyuki Sakuma,et al. Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip. , 2000 .
[3] Mitsumasa Koyanagi,et al. Real-time microvision system with three-dimensional integration structure , 1996, 1996 IEEE/SICE/RSJ International Conference on Multisensor Fusion and Integration for Intelligent Systems (Cat. No.96TH8242).
[4] Mitsumasa Koyanagi,et al. Tungsten Through-Si Via (TSV) Technology for Three-Dimensional LSIs , 2007 .
[5] Mitsumasa Koyanagi,et al. A New Three-Dimensional Multiport Memory for Shared Memory in High Performance Parallel Processor System , 1996 .
[6] Mitsumasa Koyanagi,et al. A new multiport memory for high performance parallel processor system with shared memory , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.
[7] K. Warner,et al. Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[8] Ki-Tae Park,et al. Neuromorphic vision chip fabricated using three-dimensional integration technology , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[9] R. Augur,et al. Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs , 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).
[10] Kaustav Banerjee,et al. Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.
[11] Mitsumasa Koyanagi,et al. Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system , 1990 .
[12] C.K. Chen,et al. A wafer-scale 3-D circuit integration technology , 2006, IEEE Transactions on Electron Devices.
[13] T. Nakamura,et al. Intelligent image sensor chip with three dimensional structure , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
[14] M. Koyanagi,et al. Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections , 2006, IEEE Transactions on Electron Devices.
[15] M. Koyanagi,et al. Three-Dimensionally Stacked Analog Retinal Prosthesis Chip , 2004 .
[16] Mitsumasa Koyanagi,et al. Optically Coupled Three-Dimensional Common Memory with Novel Data Transfer Method , 1989 .
[17] 福島 誉史. New Three-Dimensional Integration Technology Using Self-Assembly Technique , 2005 .
[18] H. Kikuchi,et al. New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique , 2007, 2007 IEEE International Electron Devices Meeting.
[19] Mitsumasa Koyanagi,et al. Parallel image processing field programmable gate array for real time image processing system , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).
[20] Mitsumasa Koyanagi,et al. Future system-on-silicon LSI chips , 1998, IEEE Micro.
[21] Mitsumasa Koyanagi. Progress of Three-Dimensional Integration Technology , 2000 .
[22] M. Koyanagi,et al. New Three-Dimensional Wafer Bonding Technology Using the Adhesive Injection Method. , 1998 .
[23] K. W. Lee,et al. Three-dimensional shared memory fabricated using wafer stacking technology , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).
[24] Anna W. Topol,et al. Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication , 2002, Digest. International Electron Devices Meeting,.
[25] M. Koyanagi,et al. Three-Diensional Integration Technology Based on Wafer Bonding Technique Using Micro-Bumps , 1995 .
[26] M. Koyanagi,et al. Novel Retinal Prosthesis System with Three Dimensionally Stacked LSI Chip , 2006, 2006 European Solid-State Device Research Conference.
[27] Hiroyuki Kurino,et al. Biologically Inspired Vision Chip with Three Dimensional Structure , 2001 .
[28] Mitsumasa Koyanagi,et al. Filling of Tungsten into Deep Trench Using Time-Modulation CVD Method , 2001 .
[29] P. Ramm,et al. InterChip via technology for vertical system integration , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).