Delay insertion method in clock skew scheduling
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[1] Eric R. Zieyel. Operations research : applications and algorithms , 1988 .
[2] Baris Taskin,et al. Linear timing analysis of SOC synchronous circuits with level-sensitive latches , 2002, 15th Annual IEEE International ASIC/SOC Conference.
[3] Andreas Kuehlmann,et al. Multi-Domain Clock Skew Scheduling , 2003, ICCAD 2003.
[4] Jens Vygen,et al. Clock Scheduling and Clocktree Construction for High Performance ASICS , 2003, ICCAD 2003.
[5] Shih-Hsu Huang,et al. Clock Period Minimization of Non-Zero Clock Skew Circuits , 2003, ICCAD.
[6] Shu-Cherng Fang,et al. Linear Optimization and Extensions: Theory and Algorithms , 1993 .
[7] Trevor N. Mudge,et al. CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[8] Sachin S. Sapatnekar,et al. Clock Skew Optimization , 1999 .
[9] David Harris,et al. Skew-Tolerant Circuit Design , 2000 .
[10] Marios C. Papaefthymiou,et al. Edge-triggering vs. two-phase level-clocking , 1993 .
[11] Chak-Kuen Wong,et al. A timing analysis algorithm for circuits with level-sensitive latches , 1994, ICCAD '94.
[12] Baris Taskin,et al. Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew , 2002, TAU '02.
[13] Robert K. Brayton,et al. Minimum padding to satisfy short path constraints , 1993, ICCAD.
[14] Trevor N. Mudge,et al. Critical paths in circuits with level-sensitive latches , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[15] Baris Taskin,et al. Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] John A. Ludwig,et al. Analyzing cycle stealing on synchronous circuits with level-sensitive latches , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[17] Michel Dagenais,et al. On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] Baris Taskin,et al. Timing Optimization Through Clock Skew Scheduling , 2000 .
[19] K.L. Shepard,et al. A 4.6GHz resonant global clock distribution network , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[20] Kunle Olukotun,et al. Analysis and design of latch-controlled synchronous digital circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[21] C. Patrick Yue,et al. Design of a 10GHz clock distribution network using coupled standing-wave oscillators , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[22] Gerald E. Sobelman,et al. Time borrowing in high-speed functional units using skew-tolerant domino circuits , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).
[23] S. Lipa,et al. Rotary traveling-wave oscillator arrays: a new clock technology , 2001 .
[24] J. Wood,et al. Multi-gigahertz low-power low-skew rotary clock scheme , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).