On the Relation between BDDs and FDDs

Abstract Data structures for Boolean functions form an essential component of design automation tools, especially in the area of logic synthesis. The slate of the art data structure is the ordered binary decision diagram (OBDD), which results from general binary decision diagrams (BDDs), also called branching programs, by the application of ordering restrictions. In the context of EXOR-based logic synthesis another type of decision diagram (DD), called (ordered) functional decision diagram ((O)FDD), becomes important. We study the relation between (ordered, free) BDDs and FDDs. Both BDDs and FDDs result from DDs by defining the represented function in different ways. If the underlying DD is complete, the relation between these two types of interpretation can be described by a Boolean transformation τ. This allows us to relate the FDD-size of ƒ and the BDD-size of τ(ƒ) also in the case where the corresponding DDs are free or ordered, but not (necessarily) complete. We use this property to derive several results on the computational power of OFDDs and OBDDs. Symmetric functions are shown to have efficient representations as OBDDs and OFDDs as well. Classes of functions are given that have exponentially more concise OFDDs than OBDDs, and vice versa. Finally, we determine the complexity of some standard operations if OFDDs are used for the representation of Boolean functions.

[1]  Rolf Drechsler,et al.  Testability of circuits derived from functional decision diagrams , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[2]  Yung-Te Lai,et al.  Edge-valued binary decision diagrams for multi-level hierarchical verification , 1992, DAC '92.

[3]  Wei Wan,et al.  A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[4]  Vojtech Rödl,et al.  Two lower bounds for branching programs , 1986, STOC '86.

[5]  Marek Perkowski,et al.  Design For Testability Properties of AND/XOR Networks , 1993 .

[6]  Shin-ichi Minato,et al.  Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.

[7]  Bernd Becker,et al.  On Variable Ordering of Ordered Functional Decision Diagrams , 1994 .

[8]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[9]  Christoph Meinel,et al.  Modified Branching Programs and Their Computational Power , 1989, Lecture Notes in Computer Science.

[10]  Wolfgang Rosenstiel,et al.  FDD based technology mapping for FPGA , 1992, Proceedings Euro ASIC '92.

[11]  Ph. W. Besslich,et al.  Three-valued quasi-linear transformation for logic synthesis , 1996 .

[12]  Malgorzata Marek-Sadowska,et al.  Efficient minimization algorithms for fixed polarity AND/XOR canonical networks , 1993, [1993] Proceedings Third Great Lakes Symposium on VLSI-Design Automation of High Performance VLSI Systems.

[13]  Ingo Wegener,et al.  The complexity of Boolean functions , 1987 .

[14]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[15]  Wolfgang Rosenstiel,et al.  Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.

[16]  Harold Fleisher,et al.  A Computer Algorithm for Minimizing Reed-Muller Canonical Forms , 1987, IEEE Transactions on Computers.

[17]  C. Y. Lee Representation of switching circuits by binary-decision programs , 1959 .

[18]  Wolfgang Rosenstiel,et al.  Efficient graph-based computation and manipulation of functional decision diagrams , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[19]  Ingo Wegener,et al.  Optimal Decision Trees and One-Time-Only Branching Programs for Symmetric Boolean Functions , 1984, Inf. Control..

[20]  Christoph Meinel,et al.  Efficient Analysis and Manipulation of OBDDs can be Extended to Read-once-only Branching Programs , 1992, Universität Trier, Mathematik/Informatik, Forschungsbericht.

[21]  F. Brglez,et al.  A neutral netlists of 10 combinational circuits and a target translator in FORTRAN , 1985 .

[22]  Ingo Wegener,et al.  Graph Driven BDDs - A New Data Structure for Boolean Functions , 1995, Theor. Comput. Sci..

[23]  Bernd Becker,et al.  Fast OFDD based minimization of fixed polarity Reed-Muller expressions , 1994, EURO-DAC '94.

[24]  Randal E. Bryant,et al.  On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.

[25]  Richard Rudell Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.

[26]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[27]  Elwyn R. Berlekamp,et al.  Algebraic coding theory , 1984, McGraw-Hill series in systems science.

[28]  J. M. Saul Logic synthesis for arithmetic circuits using the Reed-Muller representation , 1992, [1992] Proceedings The European Conference on Design Automation.

[29]  Rolf Drechsler,et al.  Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.

[30]  David Pellerin,et al.  Practical Design Using Programmable Logic , 1991 .

[31]  Rolf Drechsler,et al.  Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[32]  Rolf Drechsler,et al.  OFDD based minimization of fixed polarity Reed-Muller expressions using hybrid genetic algorithms , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[33]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[34]  Marek A. Perkowski,et al.  Fast minimization of mixed-polarity AND/XOR canonical networks , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[35]  Christoph Meinel,et al.  Analysis and Manipulation of Boolean Functions in Terms of Decision Graphs , 1992, WG.