Multigig lossless data compression device

This paper presents a novel lossless data compression device that extends enterprise network to branch offices by integrating multiple communication technologies. The presented device incorporates Gigabit Ethernet, STM1/STM4/STM16 interfaces for WAN connectivity, fiber channel interfaces for storage area network and 10G Ethernet interface for enterprise network connectivity. The device implements a novel architecture that implements the LZ77 lossless data compression algorithm in hardware. The high throughput data compression architecture enables the interfacing of the diverse high-speed communication technologies besides preserving the channel bandwidth for accommodating multiple applications. The device finds consumer applications to optimize WAN bandwidth, healthcare, media&broadcasting and storage area networks (SAN).

[1]  David A. Huffman,et al.  A method for the construction of minimum-redundancy codes , 1952, Proceedings of the IRE.

[2]  Solomon W. Golomb,et al.  Run-length encodings (Corresp.) , 1966, IEEE Trans. Inf. Theory.

[3]  Abraham Lempel,et al.  A universal algorithm for sequential data compression , 1977, IEEE Trans. Inf. Theory.

[4]  Terry A. Welch,et al.  A Technique for High-Performance Data Compression , 1984, Computer.

[5]  James A. Storer,et al.  Parallel algorithms for data compression , 1985, JACM.

[6]  Ian H. Witten,et al.  Arithmetic coding for data compression , 1987, CACM.

[7]  James A. Storer,et al.  A Parallel Architecture for High-Speed Data Compression , 1991, J. Parallel Distributed Comput..

[8]  S. Jones,et al.  100 Mbit/s adaptive data compressor design using selectively shiftable content-addressable memory , 1992 .

[9]  Nagarajan Ranganathan,et al.  High-speed VLSI designs for Lempel-Ziv-based data compression , 1993 .

[10]  Chen-Yi Lee,et al.  High-throughput data compressor designs using content addressable memory , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[11]  C.-Y. Lee,et al.  High-throughput data compressor designs using content addressable memory , 1995 .

[12]  Dzung Tien Hoang,et al.  Fast and efficient algorithms for text and video compression , 1997 .

[13]  Cheng-Wen Wu,et al.  Unified VLSI systolic array design for LZ data compression , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Ioannis Papaefstathiou.  Titan II: an IPcomp processor for 10-Gbps networks , 2004, IEEE Design & Test of Computers.

[15]  S.A. Khan,et al.  High Speed Lossless Data Compression Architecture , 2006, 2006 IEEE International Multitopic Conference.

[16]  W. Bishop,et al.  FPGA-Based Lossless Data Compression using Huffman and LZ77 Algorithms , 2007, 2007 Canadian Conference on Electrical and Computer Engineering.

[17]  Ioannis Papaefstathiou,et al.  Titan-R: A Reconfigurable Hardware Implementation of a High-Speed Compressor , 2008, 2008 16th International Symposium on Field-Programmable Custom Computing Machines.

[18]  Habibullah Jamal,et al.  A navigation device with MAC supporting multiple physical networks for extended coverage and operations , 2008, IEEE Transactions on Consumer Electronics.

[19]  Habibullah Jamal,et al.  Cognitive communication device for vehicular networking , 2009, IEEE Transactions on Consumer Electronics.

[20]  Bilişim.  Run-Length Encoding , 2010 .