Performance Analysis of 32 Bit Array Multiplier with a Carry Look-Ahead Adder and with a Carry Save Adder

This paper presents a technology based on the performance analysis of 32-bit array multiplier with a CSA and a CLA. Here, designs of two different array multipliers are presented, one of them using carry look-ahead adder logic for addition of partial product terms and another by introducing carry save adder in partial products lines. This architecture is shown to produce the result of addition using minimum number of logic gates. The multipliers presented are all modeled using verilog for 32-bit unsigned data. The comparison is done on the basis of three performance parameters i.e., speed, area and power consumption .To design, in terms of IC, area, speed and power has become a challenging task in VLSI design field. Our design has shown a tremendous improvement in all these performance parameters. P. Kaviya