Contrôle matériel des systèmes partiellement reconfigurables sur FPGA : de la modélisation à l'implémentation. (Hardware Control of partially reconfigurable FPGA-systems: from modeling to implementation)

Ce travail propose une methodologie de conception du controle pour les systemes reconfigurables sur FPGA, visant a ameliorer la productivite des concepteurs et assurer l'efficacite de l'implementation. Cette methodologie est basee sur un modele de controle semi-distribue qui se compose d'un ensemble de controleurs distribues modulaires assurant chacun les tâches d'observation, de prise de decision et de reconfiguration pour une region reconfigurable du systeme, et d'un coordinateur entre les decisions des controleurs distribues afin de respecter les contraintes et objectifs globaux du systeme. Cette prise de decision semi-distribuee est basee sur le formalisme des automates de modes. Cette combinaison entre modularite, division du controle et formalisme permet d'ameliorer la flexibilite, reutilisabilite et scalabilite de la conception du controle. Un autre point peut etre ajoute a cette combinaison pour ameliorer la productivite des concepteurs, qui est l'automatisation. Pour cela, la methodologie proposee est basee sur une approche d'Ingenierie Dirigee par les Modeles permettant d'automatiser la generation du code a partir de modeles de haut-niveau d'abstraction. Cette approche fait usage du profil standard MARTE (Modeling and Analysis of Real-Time and Embedded Systems), permettant de rendre les details techniques de bas niveau transparents aux concepteurs et d'automatiser la generation du code VHDL pour une implementation materielle des systemes de controle modelises afin d'assurer leur performance. Les systemes de controle generes ont ete valides par simulation. Les resultats de synthese ont montre un cout acceptable en termes de temps d'execution et de ressources pour des systemes ayant differents nombres de controleurs. Un systeme de controle compose de quatre controleurs et d'un coordinateur a ete egalement valide par implementation physique dans un systeme FPGA pour une application de traitement d'images.

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