Task data Optimization allocation with Data Migration

Chip Multi-Processors (CMPs) is applied in the embedded system. An embedded system with more cores means that there will be token more size and consumed more power. Scathed-Pad Memory (SPM) and Non-Volatile Memory (NVM) are new memory technologies. The embedded system can reduce its size and power consumption, which employ the SPM and the NVM. In this paper, we propose a Task data Optimization allocation with Data Migration algorithm (TODMA). Data migration and dynamic programming are combined to allocating task data, which has the dependency between them, in the TOMDMA algorithm. The Experimental results show that the TODMA algorithm can reduce time costs and the number of write activities on NVM by 36.25% and 24.58% respectively, and lower 34.41% systems energy consumption comparing to greedy algorithm And comparing to IDOA, the corresponding reduction are 33.82% , 10.00% and 24.27%.

[1]  Zhiping Jia,et al.  Data Allocation for Embedded Systems with Hybrid On-Chip Scratchpad and Caches , 2013, 2013 IEEE 10th International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing.

[2]  Sumesh Udayakumaran,et al.  Compiler-decided dynamic memory allocation for scratch-pad based embedded systems , 2003, CASES '03.

[3]  Yuan Xie,et al.  Endurance-aware cache line management for non-volatile caches , 2014, TACO.

[4]  Wei-Che Tseng,et al.  Write activity reduction on non-volatile main memories for embedded chip multiprocessors , 2013, TECS.

[5]  Naehyuck Chang,et al.  Energy- and endurance-aware design of phase change memory caches , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[6]  Xiaoxia Wu,et al.  Hybrid cache architecture with disparate memory technologies , 2009, ISCA '09.

[7]  Mahmut T. Kandemir,et al.  Compiler-guided leakage optimization for banked scratch-pad memories , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Edwin H.-M. Sha,et al.  Optimizing Data Placement of Loops for Energy Minimization with Multiple Types of Memories , 2013, J. Signal Process. Syst..

[9]  Narayanan Vijaykrishnan,et al.  A low-power phase change memory based hybrid cache architecture , 2008, GLSVLSI '08.

[10]  Ivo Bolsens,et al.  Proceedings of the conference on Design, Automation & Test in Europe , 2000 .

[11]  HuJingtong,et al.  Write activity reduction on non-volatile main memories for embedded chip multiprocessors , 2013 .

[12]  Yiran Chen,et al.  Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[13]  Cong Xu,et al.  NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Wei-Che Tseng,et al.  Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory , 2011, 2011 Design, Automation & Test in Europe.

[15]  Hiroaki Takada,et al.  Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems , 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[16]  Preeti Ranjan Panda,et al.  Integrating software caches with scratch pad memory , 2012, CASES '12.

[17]  Liang Shi,et al.  Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systems , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

[18]  Preeti Ranjan Panda,et al.  SPM-Sieve: A framework for assisting data partitioning in scratch pad memory based systems , 2013, 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES).