Detection of asymmetric aging-critical voltage conditions in analog power-down mode

In this work, a new verification method for the power-down mode of analog circuit blocks is presented. In power-down mode, matched transistors can be stressed with asymmetric voltages. This will cause time-dependent mismatch due to transistor aging. In order to avoid reliability problems, a new method for automatic detection of asymmetric power-down stress conditions is presented. Therefore, power-down voltage-matching rules are formulated. The method combines structural analysis and voltage propagation. Experimental results demonstrate the efficiency and effectiveness of the approach.

[1]  Georges G. E. Gielen,et al.  Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[2]  S. Blieck,et al.  Software Check for Power-Down Mode of Analog Circuits , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[3]  Chih Sieh Teng,et al.  Mismatch drift: a reliability issue for analog MOS circuits , 1992, 30th Annual Proceedings Reliability Physics 1992.

[4]  Ulf Schlichtmann,et al.  The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Michal Rewienski,et al.  A Perspective on Fast-SPICE Simulation Technology , 2011 .

[6]  Anthony S. Oates,et al.  Stress-induced MOSFET mismatch for analog circuits , 2001, 2001 IEEE International Integrated Reliability Workshop. Final Report (Cat. No.01TH8580).

[7]  Matthew Hogan.  Reduce Verification Complexity In Low/Multi-Power Designs , 2013 .

[8]  Helmut Graeb,et al.  Verification of the power-down mode of analog circuits by structural voltage propagation , 2014 .

[9]  Dina Medhat,et al.  Static low power verification at transistor level for SoC design , 2012, ISLPED '12.

[10]  Helmut E. Graeb,et al.  MARS: Matching-Driven Analog Sizing , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  A. Hastings.  The Art of Analog Layout , 2000 .