A process for detecting defects in complicated patterns

A method of detecting defects in complicated patterns such as printed circuit boards is described. This method employs two-dimensional nonlinear logical filtering. In the first stage, small portions of the pattern are extracted as potential examples of the defects. These examples include small portions near the boundary of the pattern which are due to the unevenness caused by spatial digitizing. The subsequent process eliminates these small portions on the boundary, thus leaving only the real defects. This method operates without using any prememorized standard patterns and, instead, utilizes a pseudo-standard pattern generated from the input pattern itself. This eliminates the positioning problem between the input and the standard pattern, as well as the need for any memory for the pattern. The effectiveness of this method was confirmed by digital computer simulation, and afterward, a defect extraction device was developed. This device makes it possible to detect the defects in complicated patterns in a real-time mode. It therefore has promise in facilitating the automation of tedious visual inspection processes such as those for printed circuit boards.