SURVEY OF PROCESSORS FOR SPACE

Processors for space are required to be tolerant to the following radiation and environmental effects: TID (100300 kRad for GEO and beyond, 10-50 kRad for some LEO missions), Latch-up, SEU, SET, SEFI, and temperature cycles. Another reliability issue is the complete and permanent failure of a processor or a critical sub-component. None of the methods surveyed here mitigate such failures, and the common mitigation method is based on deploying spare computers in combination with either a central reconfiguration circuit or a distributed recovery mechanism.

[1]  Pascal Traverse,et al.  AIRBUS A320/A330/A340 electrical flight controls - A family of fault-tolerant systems , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[2]  Akira Miura,et al.  Index: piggy-back satellite for aurora observation and technology demonstration , 2001 .

[3]  Michael N. Lovellette,et al.  Strategies for fault-tolerant, space-based computing: Lessons learned from the ARGOS testbed , 2002, Proceedings, IEEE Aerospace Conference.

[4]  F. Irom,et al.  Space processor radiation mitigation and validation techniques for an 1,800 MIPS processor board , 2003, Proceedings of the 7th European Conference on Radiation and Its Effects on Components and Systems, 2003. RADECS 2003..

[5]  Hiroki Hihara,et al.  CRAFT: AN EXPERIMENTAL FAULT TOLERANT COMPUTER SYSTEM FOR SERVIS-2 SATELLITE , 2003 .

[6]  K. Brieß,et al.  Fault Tolerance and COTS: Next Generation of High Performance Satellite Computers , 2003 .

[7]  Massimo Violante,et al.  A new software-based technique for low-cost fault-tolerant application , 2003, Annual Reliability and Maintainability Symposium, 2003..

[8]  Michel Pignol.  DMT and DT2: two fault-tolerant architectures developed by CNES for COTS-based spacecraft supercomputers , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[9]  Han-xu Sun,et al.  The New Fault Tolerant Onboard Computer for Microsatellite Missions , 2006 .

[10]  Michel Pignol,et al.  A Testbench for Validation of DST Fault-Tolerant Architectures on PowerPC G4 COTS Microprocessors , 2011 .