Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM

Spin-transfer torque random access memory (STT-RAM) is considered as a promising candidate to replace SRAM as the next generation cache memory since it has better scalability and lower leakage power. Recently, 2-bit multi-level cell (MLC) STT-RAM has been proposed to further increase data density. However, a key drawback for MLC STT-RAM is that the magnetization directions of its hard and soft domains cannot be flipped to two opposite directions simultaneously, which leads to the two-step problem in state transitions. Two-step state transitions would significantly impact the lifetime of MLC STT-RAM due to the wasted flips in the soft domains. To solve the problem, this paper proposes a novel two-step state transition minimization (TSTM) scheme, to improve the lifetime of MLC STT-RAM when it is employed in cache design. The basic idea is by sacrificing certain cells as auxiliary flags, the two-step state transitions in STT-RAM can be well eliminated. Experimental results show that the proposed scheme can improve the lifetime of MLC STT-RAM to 318.5%.

[1]  Yuan Xie,et al.  i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[2]  Yuan Xie,et al.  Access scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and its optimization , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[3]  Jun Yang,et al.  Energy reduction for STT-RAM using early write termination , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[4]  Danghui Wang,et al.  Unleashing the potential of MLC STT-RAM caches , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[5]  Mohammad Arjomand,et al.  Architecting the Last-Level Cache for GPUs using STT-RAM Technology , 2015, ACM Trans. Design Autom. Electr. Syst..

[6]  Bruce Jacob,et al.  Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM , 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

[7]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[8]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[9]  Soontae Kim,et al.  Ternary cache: Three-valued MLC STT-RAM caches , 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

[10]  Farshad Moradi,et al.  Symmetric write operation for 1T-1MTJ STT-RAM cells using negative bitline technique , 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

[11]  Chita R. Das,et al.  Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs , 2012, DAC Design Automation Conference 2012.

[12]  Wei-Kai Cheng,et al.  A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM , 2014, ICS.

[13]  Kiyoung Choi,et al.  Lower-bits cache for low power STT-RAM caches , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[14]  Farshad Moradi,et al.  Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Yiran Chen,et al.  STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[16]  Dong Li,et al.  LastingNVCache: A Technique for Improving the Lifetime of Non-volatile Caches , 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

[17]  Yiming Huai,et al.  Spin-Transfer Torque MRAM (STT-MRAM): Challenges and Prospects , 2008 .

[18]  H. Ohno,et al.  A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions , 2010, 2010 Symposium on VLSI Technology.

[19]  Jason Cong,et al.  Static and dynamic co-optimizations for blocks mapping in hybrid caches , 2012, ISLPED '12.

[20]  Yiran Chen,et al.  On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations , 2013, JETC.

[21]  Youguang Zhang,et al.  Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology , 2015, IEEE Transactions on Electron Devices.

[22]  Yiran Chen,et al.  State-restrict MLC STT-RAM designs for high-reliable high-performance memory system , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[23]  Ahmad Patooghy,et al.  Coding Last Level STT-RAM Cache for High Endurance and Low Power , 2014, IEEE Computer Architecture Letters.

[24]  X. Lou,et al.  Demonstration of multilevel cell spin transfer switching in MgO magnetic tunnel junctions , 2008 .

[25]  Zhaohao Wang,et al.  DFSTT-MRAM: Dual Functional STT-MRAM Cell Structure for Reliability Enhancement and 3-D MLC Functionality , 2014, IEEE Transactions on Magnetics.