Design of Stable High Order 1Bit SigmaDelta Modulators

In this paper, a method for designing stable 1-bit high order (?? 3) sigma-delta modulators is presented. The stability analysis is based on the root locus and modeling the quantizer for each clock period at a time. The quantizer's gain in the modulator at the present clock period determines the modulator's stability for the next clock period. If the modulator is stable during each clock period, it is unconditionally stable and behaves as a linear A/D converter. Examples with 3rd, 4th, 5th and 6th order sigma-delta modulators are given to explore the use of the proposed method in practise. With the designed 6th order modulator it is possible to achieve 23 bit signal to quantization noise ratio at the oversampllng ratio of 64.