论文信息 - A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell

A 110 nm 512 Mb DDR DRAM with vertical transistor trench cell

This paper describes a 512 Mb DDR SDRAM in 110 nm technology based on a highly cost efficient 8F/sup 2/ trench capacitor cell with a double gate vertical pass transistor. The product also features a bitline voltage generator using a distributed output transistor with a power supply IR-drop correction scheme. A read/write selective column activation circuit is employed to optimize high frequency operation.

[1] W. Bergner,et al. A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).