Layout automation of VLSI “custom cell-based” chips consists of two main tasks : the generation of necessary layout modules (cells) in a given target technology and the cells placement & interconnections routing. In the CVS system, developed whitin the ESPRIT 802 project, these tasks are carried out by the two tools illustrated in this paper : the Flexible Block Library (FBL) and the Floor-planner (ACCORDO). ACCORDO is presented in the first part of the paper, with some detail concerning the design flow of the floor-plan generation and the strategy adopted to solve each step in this flow. The FBL approach to guarantee technology independence, flexibility and maintainability in module generation is then discussed; significant examples are given for both the tools.
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