FinFET-based SRAM design
暂无分享,去创建一个
Zheng Guo | Borivoje Nikolic | Sriram Balasubramanian | Tsu-Jae King | Radu Zlatanovici | T. King | B. Nikolić | S. Balasubramanian | R. Zlatanovici | Z. Guo
[1] C. Morganti,et al. The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium/sup /spl reg//-family processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[2] E. Seevinck,et al. Static-noise margin analysis of MOS SRAM cells , 1987 .
[3] Andrew R. Brown,et al. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .
[4] M. Bohr,et al. A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).
[5] K. Roy,et al. Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[6] N. Vallepalli,et al. A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[7] C. Hu,et al. Sub-50 nm P-channel FinFET , 2001 .
[8] M. Motoyoshi,et al. A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18 /spl mu/m generation and desirable for ultra high speed operation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[9] J. Meindl,et al. The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.
[10] I. Aller,et al. FinFET SRAM for high-performance low-power applications , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).
[11] A. Vandooren,et al. CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET) , 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).
[12] M. Yamaoka,et al. Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).
[13] Jan M. Rabaey,et al. SRAM leakage suppression by minimizing standby supply voltage , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[14] J. Kedzierski,et al. A functional FinFET-DGCMOS SRAM cell , 2002, Digest. International Electron Devices Meeting,.
[15] Michel Haond,et al. Validated 90nm CMOS technology platform with low-k copper interconnects for advanced system-on-chip (SoC) , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).
[16] Kaushik Roy,et al. Leakage and process variation effects in current testing on future CMOS circuits , 2002, IEEE Design & Test of Computers.
[17] H.-S.P. Wong,et al. Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[18] S. Natarajan,et al. SE5 - SRAM design in the nanoscale era , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
[19] O. Gluschenkov,et al. Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics , 2003, IEEE Electron Device Letters.