A study of stacking limit and scaling in 3D ICs: an interconnect perspective

An examination of large-scale stacking of 3D integrated ICs from a power-supply and thermal reliability perspective is presented. Noise characteristics and scaling issues related to through-silicon-via (TSV) size and pitch as well as other power-supply topology characteristics are included. Thermal simulations are carried out assuming the use of micro-fluidic heatsinks to provide cooling to systems with power dissipation of up to 525 watts and 46 integrated silicon tiers. Results indicate that these large systems are feasible given sufficient planning. Power-delivery-bump pitch is identified as the most important factor influencing IR-drop and dynamic noise. Contact resistance also may become a major limiting factor.

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