The realization of plasmo-electronic integrated circuits in a silicon chip will be enabled by two new plasmonic materials that are proposed and modeled in this article. The first is ion-implanted Si (n-type or p-type) at the surface of an intrinsic Si chip. The second is a thin-layer silicide such as Pd(2)Si, NiSi, PtSi(2) WSi(2) or CoSi(2) formed at the Si chip surface. For doping concentrations of 10(20) cm(-3) and 10(21) cm(-3), our dispersion calculations show that bound surface plasmon polaritons will propagate with low loss on stripe-shaped plasmonic waveguides over the 10 to 55 microm and 2.8 to 15 microm wavelength ranges, respectively. For Pd(2)Si/Si plasmonic waveguides, the wavelength range of 0.5 to 7.5 microm is useful and here the propagation lengths are 1 to 2300 microm. For both doped and silicided guides, the SPP mode field extends much more into the air above the stripe than it does into the conductive stripe material.
[1]
Jesper Jung,et al.
Scaling for gap plasmon based waveguides.
,
2008,
Optics express.
[2]
N I Zheludev,et al.
Generation of traveling surface plasmon waves by free-electron impact.
,
2006,
Nano letters.
[3]
Richard A. Soref,et al.
Toward silicon-based longwave integrated optoelectronics (LIO)
,
2008,
SPIE OPTO.
[4]
Ewold Verhagen,et al.
Direct imaging of propagation and damping of near-resonance surface plasmon polaritons using cathodoluminescence spectroscopy
,
2006
.
[5]
Erich Gornik,et al.
Thermal Excitation of Two-Dimensional Plasma Oscillations
,
1982
.