Analysis of multibackground memory testing techniques
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[1] John P. Hayes,et al. Detection oF Pattern-Sensitive Faults in Random-Access Memories , 1975, IEEE Transactions on Computers.
[2] Yu-Jen Huang,et al. Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories , 2006, Eleventh IEEE European Test Symposium (ETS'06).
[3] Yervant Zorian,et al. Embedded-memory test and repair: infrastructure IP for SoC yield , 2003, IEEE Design & Test of Computers.
[4] A. J. van de Goor,et al. Testing Semiconductor Memories: Theory and Practice , 1998 .
[5] A. Kablanian. Embedded Memory Test and Repair , 2002, MTDT.
[6] Kewal K. Saluja,et al. Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Svetlana V. Yarmolik. Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests , 2008, Int. J. Appl. Math. Comput. Sci..
[8] Ireneusz Mrozek,et al. Optimal Backgrounds Selection for Multi Run Memory Testing , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.
[9] Ireneusz Mrozek,et al. Multi Background Memory Testing , 2007, MIXDES 2007.
[10] Mark G. Karpovsky,et al. Pseudo-exhaustive word-oriented DRAM testing , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[11] Jack D. Tubbs,et al. A note on binary template matching , 1989, Pattern Recognit..
[12] I. Voyiatzis,et al. Accumulator - based compression in symmetric transparent RAM BIST , 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..
[13] J. Sosnowski,et al. Improving Software Based Self - Testing for Cache Memories , 2007, 2007 2nd International Design and Test Workshop.
[14] Andrzej Krasniewski. Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.
[15] Ireneusz Mrozek,et al. Multi Background Memory Testing , 2007, 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems.
[16] J. Otterstedt,et al. Integration of non-classical faults in standard March tests , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).
[17] Michael Nicolaidis,et al. Theory of Transparent BIST for RAMs , 1996, IEEE Trans. Computers.
[18] Sargur N. Srihari,et al. Binary Vector Dissimilarity Measures for Handwriting Identification , 2003, IS&T/SPIE Electronic Imaging.
[19] Cheng-Wen Wu,et al. Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Bruce F. Cockburn. Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs , 1995, Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing.
[21] I. Mrozek,et al. MATS+ transparent memory test for Pattern Sensitive Fault detection , 2008, 2008 15th International Conference on Mixed Design of Integrated Circuits and Systems.
[22] John P. Hayes. Testing Memories for Single-Cell Pattern-Sensitive Faults , 1980, IEEE Transactions on Computers.
[23] Mark G. Karpovsky,et al. Transparent memory testing for pattern sensitive faults , 1994, Proceedings., International Test Conference.
[24] Svetlana V. Yarmolik,et al. Address sequences for march tests to detect pattern sensitive faults , 2006, Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06).