Optimizing cost and thermal performance: rapid prototyping of a high pin count cavity-up enhanced plastic ball grid array (EPBGA) package

A three-dimensional finite element model of a 420 lead (5 row perimeter) cavity-up enhanced plastic ball grid array (EPBGA) package was developed using the ANSYS/sup TM/ finite element simulation code. The developed model was utilized to perform a sensitivity analysis in order to quantify the effects of varying package and system motherboard designs. Design variables included: (1) chip size; (2) package substrate metallized plane layers; (3) motherboard metallized plane layers; (4) inner solder ball matrix and vias; (5) package aluminum heat spreader thickness; and (6) chip power dissipation. Predicted package junction-to-ambient thermal resistance (/spl theta//sub JA/) values were used in conjunction with a central composite design of experiments to develop a response surface equation which quickly predicts EPBGA package thermal performance as a function of the six design variables. The methodology described allows for rapid analysis of design options in the "dynamic" environment of prototyping, and the implementation of optimized cost effective package designs to meet required standards under multiple customer environments.

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