An automatic test bench generation system

Presents an automatic test bench generation system for VHDL behavioral models. The Modeler's Assistant, an interactive CAD tool developed at Virginia Tech, gives the graphical representation of a VHDL behavioral model, called a process model graph (PMG). The process test generator (PTG) is used to generate the stimulus/response test sets for individual processes of a PMG. The hierarchical behavioral test generator (HBTG) accepts the PMG and the test sets produced by PTG as inputs, and then hierarchically constructs a test sequence for the entire model. The test sequence is converted into a test bench by the test bench generator (TBG), and it is then used for simulation of the model. Experimental results show that the test benches generated exercise the models thoroughly.<<ETX>>

[1]  Jacob A. Abraham,et al.  Speed up of test generation using high-level primitives , 1991, DAC '90.

[2]  Gerd Krüger,et al.  A tool for hierarchical test generation , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  John P. Hayes,et al.  Hierarchical test generation using precomputed testsd for modules , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[4]  John P. Hayes,et al.  Hierarchical test generation using precomputed tests for modules , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  James R. Armstrong,et al.  The Modeler's Assistant: A CAD Tool for Behavioral Model Development , 1993, CHDL.

[6]  Tohru Sasaki,et al.  A High Level Test Pattern Generation Algorithm , 1983, ITC.

[7]  H. D. Hümmer,et al.  Functional Tests for Hardware Derived from VHDL Description , 1991 .

[8]  Hans G. Kerkhoff,et al.  Hierarchical test-pattern generation , 1990 .

[9]  Alfred V. Aho,et al.  Data Structures and Algorithms , 1983 .

[10]  F. E. Norrod,et al.  An Automatic Test Generation Algorithm for Hardware Description Languages , 1989, 26th ACM/IEEE Design Automation Conference.

[11]  Michael H. Schulz,et al.  A hierarchical test pattern generation system based on high-level primitives , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  J. R. Armstrong,et al.  Hierarchical test generation for VHDL behavioral models , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[13]  James R. Armstrong,et al.  VHDL Semantics for Behavioral Test Generation , 1991 .