Proposed architecture for an FPGA configuration for a payload module computer

This paper introduces an Field Programmable Gate Array (FPGA) configuration architecture for the use on an FPGA based Payload Module Computer (PMC) on a satellite. This architecture was developed during the small satellite project “Flying Laptop”. The challenge was to have a short development time to enable early testing of the payloads and the interfaces to the On-Board Computer (OBC), but simultaneously retaining the ability to extend the configuration with different data routing and data processing algorithms. As a result the configuration is divided into two layers. In the first layer, the controlling layer, commands and telemetry is exchanged between the OBC and the payloads. At this layer the Payload Module Computer (PMC) mainly functions as a router. The second layer is called the data handling layer. Within this layer data is transferred from any data source to any data sink in pipelining mode. Using an FPGA this routing happens in parallel for as many payloads as desired. The routing of payload data, as well as the enabling and disabling of data processing cores, is configurable during runtime. All payload handlers, as well as data processing cores, have a straightforward and standardized interface. This enables an easy exchange of future data processing cores or even an addition or exchange of payloads. With the proposed architecture a foundation for the development of FPGA configurations for PMCs is established. Utilizing this architecture introduces a way to test payloads early without the need to write extra code for testing. The customizable data routing during run time leads to easier testing of new cores and handlers, due to the easy usage of debug output ports. Also in case of a damaged memory chip the data can easily be rerouted to a healthy chip. Adding or exchanging multiple data processing cores or payloads at any time is easy, which results in a flexible architecture.