AN EFFICIENT VITERBI DECODER

Convolutional encoding with Viterbi decoding is a good forward error correction technique suitable for channels affected by noise degradation. Fangled Viterbi decoders are variants of Viterbi decoder (VD) which decodes quicker and takes less memory with no error detection capability. Modified fangled takes it a step further by gaining one bit error correction and detection capability at the cost of doubling the computational complexity and processing time. A new efficient fangled Viterbi algorithm is proposed in this paper with less complexity and processing time along with 2 bit error correction capabilities. For 1 bit error correction for 14 bit input data, when compared with Modified fangled Viterbi decoder, computational complexity has come down by 36-43% and processing delay was halved. For a 2 bit error correction, when compared with Modified fangled decoder computational complexity decreased by 2236%.

[1]  Chaitali Chakrabarti,et al.  An approach for adaptively approximating the Viterbi algorithm to reduce power consumption while decoding convolutional codes , 2004, IEEE Transactions on Signal Processing.

[2]  H. Kobayashi,et al.  DVD players using a Viterbi decoding circuit , 1997, ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348).

[3]  Paul Chow,et al.  RACER: a reconfigurable constraint-length 14 Viterbi decoder , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[4]  K. Dimyati,et al.  Improving FEC Performance for Baseband Signal Processing using a Lookup Table , 2005, 2005 5th International Conference on Information Communications & Signal Processing.

[5]  D. Perels,et al.  FPGA Implementation of Viterbi Decoders for MIMO-BICM , 2005, Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005..

[6]  Jang-Hyun Park,et al.  Performance test of Viterbi decoder for wideband CDMA system , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[7]  Viktor K. Prasanna,et al.  Time and energy efficient Viterbi decoding using FPGAs , 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

[8]  I. M. Onyszchuk.  Coding gains and error rates from the Big Viterbi Decoder , 1991 .

[9]  Yiqun Zhu,et al.  A Novel High-Speed Configurable Viterbi Decoder for Broadband Access , 2003, EURASIP J. Adv. Signal Process..

[10]  J. Heller,et al.  A New Coding Technique for Asynchronous Multiple Access Communication , 1971 .

[11]  Gert Cauwenberghs,et al.  Integrated 64-state parallel analog Viterbi decoder , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[12]  M. Omair Ahmad,et al.  FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  T. Sansaloni,et al.  Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder , 2008, J. Signal Process. Syst..

[14]  J. Isoaho,et al.  Design and Implementation of Viterbi Decoder with FPGAs , 1999, J. VLSI Signal Process..

[15]  S. Hema,et al.  FPGA implementation of Viterbi decoder , 2007 .

[16]  Andrew J. Viterbi,et al.  Error bounds for convolutional codes and an asymptotically optimum decoding algorithm , 1967, IEEE Trans. Inf. Theory.

[17]  J.R. Cavallaro,et al.  A reconfigurable Viterbi decoder architecture , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[18]  I. Abou-Faycal,et al.  A fast maximum-likelihood decoder for convolutional codes , 2002, Proceedings IEEE 56th Vehicular Technology Conference.

[19]  Harald Haas,et al.  Asilomar Conference on Signals, Systems, and Computers , 2006 .

[20]  Dennis Goeckel,et al.  A dynamically reconfigurable adaptive viterbi decoder , 2002, FPGA '02.

[21]  T.A. Kwasniewski,et al.  High-speed Viterbi decoder for W-LAN and broadband applications , 2004, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..