Implementation aspects of fault-tolerant logic built with single-electron devices

This paper presents a single-electron tunneling (SET) device implementation of gates needed to build a nanoscale logic array for fault-tolerant computing. The proposed architecture is based on a regular array of locally interconnected SET gates controlled by CMOS peripheries. Embedded hardware and information redundancies help to surmount the limited reliability of nanodevices. Such a logic system can be versatile due to binary programmable interconnections. Gate structures designed for SET technology are presented and their simulation results are discussed.

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