A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with −97.7dBc THD and 80dB DR using low-latency DEM

Due to their inherent anti-aliasing properties and potential for low-power design, continuous-time (CT) ΔΣ ADCs are an indispensable component in wireless communication systems such as GSM/WCDMA, since a precise sampling network is not required. However, conventional CT ΔΣ ADCs suffer from 2 main problems: 1) high sensitivity to clock jitter, and 2) excess loop delay stemming from quantizer and DEM latency. To tackle the first problem, an NRZ multi-bit DAC can be used to trade achievable SNR with an increased number of DAC levels [1–3]. The NRZ nature dictates the addition of deliberate z−1 or z−1/2 terms in the loop to accommodate delay from the quantizer and DEM, which in turn requires a local feedback DAC around the quantizer to stabilize the loop. However, ISI-induced distortion remains prominent. A 1b SC DAC is used in [4] for low jitter sensitivity and elimination of DEM, at the expense of limited input range.