Electrical assessment of copper damascene interconnects down to sub-50 nm feature sizes

The feasibility of fabrication of sub-50 nm copper interconnects was demonstrated. A process flow to obtain wires with line widths far below the limits given by lithography using a removable spacer technique was developed for copper damascene lines. The behavior of the electrical resistivity of lines with feature sizes down to 43 nm was investigated for temperatures ranging from 80 to 573 K. An increase of the electrical resistivity with shrinking dimensions was observed as a result of size effects. The experimental data will be discussed in detail and can be well described by a contribution of electron surface scattering and grain-boundary scattering. The results clearly demonstrate that cooling of Cu wires will no longer help to maintain low electrical resistivity in the mesoscopic regime, i.e. when feature sizes of metal wires approach the mean free path of the charge carriers. For future technology generations size effects, which are not explicitly addressed in the ITRS, will come into play and will become a significant contributor to wire related delay times.