Dynamics of high-frequency CMOS dividers

Frequency dividers are an essential part of broadband communications IC's. They are often the most difficult part of a circuit designed to operate at very high frequencies, especially in CMOS. In order to optimize the circuit for high frequency performance, it is necessary to understand the dynamics of the dividers. This paper presents an analysis of the dynamics of high frequency CMOS dividers and sets some guidelines for circuit design.

[1]  W. Fang,et al.  An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers , 1990 .

[2]  Keh-Chee Jen,et al.  Fully-integrated SONET OC48 transceiver in standard CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  H. Wu,et al.  A 19GHz 0.5mW 0.35mm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement , 2001 .

[4]  Rafael J. Betancourt-Zamora,et al.  1-GHz and 2.8-GHz CMOS injection-locked ring oscillator prescalers , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[5]  Michael Green,et al.  New structures for very high-frequency CMOS clock dividers , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).