DRAM industry has gained most of the interest in the memory chip industry in the last decades for its high density (due to its simple structure) and lower power consumption. As the density of DRAM chips increased, the bit-line parasitic capacitances increased and many problems appeared such as increased power consumption and larger read/write access times which gave great attention to improve the design of the CMOS sense amplifier used in the memory chip for its great effects on memory access time, overall memory power dissipation and chip density. In this paper, we introduce one of the most effective solutions to increase the performance of the advanced high density DRAMs by replacing the sense amplifier circuit with a specially designed logic buffer circuit based on Resonant Tunneling Diode (RTD) that can be fabricated in Nano-scale and exhibit higher operation speed with lower power consumption and higher chip density. The proposed design improves the Power Delay Product (PDP) by about 36% compared with that in conventional RTD-CMOS sense amplifier and 15% compared with that in conventional CMOS sense amplifier. The 45nm CMOS technology is used in this paper.
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