Multilevel test and validation of algorithms implemented in a SOPC VisionNode

This paper describes results of a tool development process and still on-going research program in multilevel algorithm design and validation for multisensor systems. Our work covers both the algorithm design process including the simulation efforts and the implementation of the algorithms into the sensor node prepared for real-time processing within a vision system network. The sensor node hardware is based on the System on Programmable Chip (SOPC)-Technology. This gives us the flexibility to interface different kinds of sensor elements (matrix-, line-sensors) and the processing-power to provide real-time possibilities in height data-rate applications. At the point today our hardware module for Vision applications also uses a CPU module. This results in a high flexibility concerning the communication efforts. Our design can provide the use of CPU-modules within the SOPC design also. Mapping algorithms into a distributed sensor network will be done in either a centralized or decentralized way. That means the algorithm will be running on one sensor node or a part of the algorithm is implemented on some others nodes within the network. Beginning at the design and simulation level different kind of levels are opened for optimization, test and validate the developed algorithm.