IDDT Testing versus IDDQ Testing

IDDQ testing has progressed to become a worldwide accepted test method to detect CMOS IC defects. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage, which is referred to IDDT testing. This letter presents a formal procedure to identify IDDT testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by IDDQ or other test methods, which shows the significance of IDDT testing.

[1]  Shyang-Tai Su,et al.  Transient power supply current monitoring—A new test method for CMOS VLSI circuits , 1995, J. Electron. Test..

[2]  Zhongcheng Li,et al.  Waveform polynomial manipulation using BDDs , 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

[3]  Yashwant K. Malaiya,et al.  Testable design for BiCMOS stuck-open fault detection , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[4]  Farid N. Najm,et al.  Transition density: a new measure of activity in digital circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Shyang-Tai Su,et al.  Transient power supply current testing of digital CMOS circuits , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[6]  Charles F. Hawkins,et al.  IDDQ testing: A review , 1992, J. Electron. Test..

[7]  Yashwant K. Malaiya,et al.  A New Fault Model and Testing Technique for CMOS Devices , 1982, International Test Conference.

[8]  Mark W. Levi,et al.  CMOS Is Most Testable , 1981, International Test Conference.

[9]  Jacob A. Abraham,et al.  BiCMOS fault models: is stuck-at adequate? , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[10]  Bapiraju Vinnakota.  Monitoring power dissipation for fault detection , 1996, Proceedings of 14th VLSI Test Symposium.