Tools for the computer-aided design of multigigahertz superconducting digital circuits

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented.

[1]  K. K. Likharev,et al.  Rapid Single-Flux-Quantum Logic , 1993 .

[2]  E. Charbon,et al.  INDEX: an inductance extractor for superconducting circuits , 1993, IEEE Transactions on Applied Superconductivity.

[3]  V. Semenov,et al.  Single flux, quantum B flip-flop and its possible applications , 1994, IEEE Transactions on Applied Superconductivity.

[4]  Steven M. Rubin,et al.  Computer Aids For VLSI Design , 1987 .

[5]  T. Nakazato,et al.  Inductance computation of microscopic superconducting loop , 1997, IEEE Transactions on Applied Superconductivity.

[6]  K. Gaj,et al.  A Cadence-based design environment for single flux quantum circuits , 1997, IEEE Transactions on Applied Superconductivity.

[7]  M.J. Feldman,et al.  Multiparameter optimization of RSFQ circuits using the method of inscribed hyperspheres , 1995, IEEE Transactions on Applied Superconductivity.

[8]  Ulrich Golze.  VLSI Chip Design with the Hardware Description Language VERILOG , 1996, Springer Berlin Heidelberg.

[9]  W. Chang,et al.  The inductance of a superconducting strip transmission line , 1979 .

[10]  G. Hachtel.  The simplicial approximation approach to design centering , 1977 .

[11]  A. Krasniewski,et al.  Design and low speed testing of a four-bit RSFQ multiplier-accumulator , 1997, IEEE Transactions on Applied Superconductivity.

[12]  Eby G. Friedman,et al.  Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits , 1997, J. VLSI Signal Process..

[13]  O. Mukhanov,et al.  Ultimate performance of the RSFQ logic circuits , 1987 .

[14]  Samir Palnitkar,et al.  Verilog HDL: a guide to digital design and synthesis , 1996 .

[15]  D.Y. Zinoviev,et al.  New RSFQ circuits (Josephson junction digital devices) , 1993, IEEE Transactions on Applied Superconductivity.

[16]  Allen M. Dewey.  Analysis and Design of Digital Systems with VHDL , 1996 .

[17]  O.A. Mukhanov,et al.  Time-to-digital converters based on RSFQ digital counters , 1997, IEEE Transactions on Applied Superconductivity.

[18]  A. Krasniewski,et al.  Logic simulation of RSFQ circuits , 1993, IEEE Transactions on Applied Superconductivity.

[19]  N. Yoshikawa,et al.  Data-driven self-timed RSFQ digital integrated circuit and system , 1997, IEEE Transactions on Applied Superconductivity.

[20]  Wojciech Maly,et al.  VLSI Design for Manufacturing: Yield Enhancement , 1989 .

[21]  V. K. Semenov,et al.  Specific problems of numerical analysis of the Josephson junction circuits , 1987 .

[22]  M. M. Khapaev.  ERRATUM: Extraction of inductances of plane thin film superconducting circuits , 1997 .

[23]  J. Satchell,et al.  Stochastic simulation of SFQ logic , 1997, IEEE Transactions on Applied Superconductivity.

[24]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[25]  P. Rott,et al.  Inductance estimation for complicated superconducting thin film structures with a finite segment method , 1997, IEEE Transactions on Applied Superconductivity.

[26]  Y. Hamazaki,et al.  Chip layout design of a Josephson LSI circuit for examining high-speed operability by using a standard cell automatic placement and routing technique , 1994, IEEE Transactions on Applied Superconductivity.

[27]  S. R. Whiteley,et al.  Josephson junctions in SPICE3 , 1991 .

[28]  H. Topfer,et al.  Design tools for parameter determination and simulation of integrated Josephson structures , 1995, IEEE Transactions on Applied Superconductivity.

[29]  Vasili K. Semenov,et al.  Preliminary results on the analog-to-digital converter based on RSFQ logic , 1996, Proceedings of 20th Biennial Conference on Precision Electromagnetic Measurements.

[30]  Kris Gaj,et al.  Functional modeling of RSFQ circuits using Verilog HDL , 1997, IEEE Transactions on Applied Superconductivity.

[31]  K. Gaj,et al.  Toward a systematic design methodology for large multigigahertz rapid single flux quantum circuits , 1999, IEEE Transactions on Applied Superconductivity.

[32]  S. R. Whiteley,et al.  Inductance calculation of 3D superconducting structures , 1999 .

[33]  S. Polonsky,et al.  PSCAN'96: new software for simulation and optimization of complex RSFQ circuits , 1997, IEEE Transactions on Applied Superconductivity.

[34]  A. Rylyakov,et al.  All-digital 1-bit RSFQ autocorrelator for radioastronomy applications: design and experimental results , 1998, IEEE Transactions on Applied Superconductivity.

[35]  V. Semenov,et al.  RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems , 1991, IEEE Transactions on Applied Superconductivity.

[36]  P. Bunyk,et al.  RSFQ microprocessor: new design approaches , 1997, IEEE Transactions on Applied Superconductivity.

[37]  T. Harnisch,et al.  Design centering methods for yield optimization of cryoelectronic circuits , 1997, IEEE Transactions on Applied Superconductivity.

[38]  C. Hamilton,et al.  Margins and yield in single flux quantum logic , 1991, IEEE Transactions on Applied Superconductivity.

[39]  Konstantin K. Likharev,et al.  Ultrafast superconductor digital electronics: RSFQ technology roadmap , 1996 .

[40]  Priyadarsan Patra,et al.  Delay insensitive logic for RSFQ superconductor technology , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[41]  J. Kunert,et al.  Formal description of the functional behavior of RSFQ logic circuits for design and optimization purposes , 1997, IEEE Transactions on Applied Superconductivity.

[42]  Konstantin K. Likharev,et al.  Superconductors speed up computation , 1997 .

[43]  M.F. Bocko,et al.  High-speed operation of a 64-bit circular shift register , 1998, IEEE Transactions on Applied Superconductivity.

[44]  F. H. Uhlmann,et al.  Inductance calculation for integrated superconducting structures by minimizing free energy , 1995, IEEE Transactions on Applied Superconductivity.

[45]  Stanislav Polonsky,et al.  PSCAN: personal superconductor circuit analyser , 1991 .

[46]  M. M. Khapaev.  Extraction of inductances of a multi-superconductor transmission line , 1996 .

[47]  T. Van Duzer,et al.  A computer-aided design framework for superconductor circuits , 1995, IEEE Transactions on Applied Superconductivity.

[48]  A. Krasniewski,et al.  A clock distribution scheme for large RSFQ circuits , 1995, IEEE Transactions on Applied Superconductivity.

[49]  O. Mukhanov,et al.  RSFQ 1024-bit shift register for acquisition memory , 1993, IEEE Transactions on Applied Superconductivity.