Simple One-to-One Architecture for Parallel Execution of Embedded Control Systems

We propose in this paper a simple architecture for efficient execution of embedded control systems using a model-based design to which automatic parallelization is also applicable. This architecture makes use of the advantages of embedded control systems in the sense of parallel execution, and reduces their disadvantages by incurring minimal overhead from task scheduling and inter-task communication. With a model predictive control application, our architecture achieves communication latency 20 times faster than in current real-time OS communication methods for many cores. Moreover, our architecture achieves a speed-up for 64 cores that is 40 times that in single core execution, while its performance scalability is saturated up to 32 cores in real-time OS communication.

[1]  Bin Xie,et al.  An energy-aware online task mapping algorithm in NoC-based system , 2011, The Journal of Supercomputing.

[2]  S. Doki,et al.  Wide rand and fast response control of PMSM by using model predictive control , 2013, 2013 IEEE 10th International Conference on Power Electronics and Drive Systems (PEDS).

[3]  Laxmikant V. Kalé,et al.  Topology-aware task mapping for reducing communication contention on large parallel machines , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

[4]  Shinji Doki,et al.  Improve torque response using the inverter overmodulation range in position sensorless control system of PMSM , 2013, IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society.

[5]  Nagisa Ishiura,et al.  Model Based Parallelization from the Simulink Models and Their Sequential C Code , 2012 .

[6]  Hironori Kasahara,et al.  Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-Power Multicore , 2011, LCPC.

[7]  E. Carvalho,et al.  Congestion-aware task mapping in heterogeneous MPSoCs , 2008, 2008 International Symposium on System-on-Chip.

[8]  Thomas Canhao Xu,et al.  Tree-model based mapping for energy-efficient and low-latency Network-on-Chip , 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[9]  Gurindar S. Sohi,et al.  Multiscalar processors , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[10]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[11]  Suleyman Tosun Cluster-based application mapping method for Network-on-Chip , 2011, Adv. Eng. Softw..

[12]  Sanjay V. Rajopadhye,et al.  OREGAMI: Tools for mapping parallel computations to parallel architectures , 1991, International Journal of Parallel Programming.

[13]  Nectarios Koziris,et al.  An efficient algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures , 2000, Proceedings 8th Euromicro Workshop on Parallel and Distributed Processing.