Performance modeling and characterization of large last level caches

For each different cache configuration, we identified parametric functions to characterize the probability density of statistics related to cache performance. Observe that, the parameters (α,β) in (1) and (a, b, n) in (2) depend on cache configuration. We next need to study the sensitivity of the parameters in the density function to cache configuration parameters. Once this is established we can express the distribution of CRT, SRT and IHT in terms of cache size and line size alongwith workload specific constants. Having known these distributions, T crt , T srt and T iht and hence m from Model-A and Model-B can be written as an explicit function of cache size and line size for a given workload.

[1]  Michel Dubois,et al.  RPM: A Rapid Prototyping Engine for Multiprocessor Systems , 1995, Computer.

[2]  Joel L. Wolf,et al.  Synthetic Traces for Trace-Driven Simulation of Cache Memories , 1992, IEEE Trans. Computers.

[3]  Vijayalakshmi Srinivasan,et al.  Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[4]  Alan Jay Smith,et al.  Cache Memories , 1982, CSUR.

[5]  Parijat Dube,et al.  Program behavior characterization in large memory systems , 2010, 2010 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS).

[6]  Babak Falsafi,et al.  Dead-block prediction & dead-block correlating prefetchers , 2001, ISCA 2001.

[7]  Babak Falsafi,et al.  ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs , 2009, TRETS.

[8]  Parijat Dube,et al.  Performance of large low-associativity caches , 2010, PERV.

[9]  Vijayalakshmi Srinivasan,et al.  On the Nature of Cache Miss Behavior: Is It √2? , 2008, J. Instr. Level Parallelism.

[10]  Babak Falsafi,et al.  Accurate and complexity-effective spatial pattern prediction , 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).

[11]  Moinuddin K. Qureshi,et al.  Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[12]  David A. Wood,et al.  A model for estimating trace-sample miss ratios , 1991, SIGMETRICS '91.

[13]  Vijayalakshmi Srinivasan,et al.  Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.

[14]  Ramendra K. Sahoo,et al.  MemorIES: a programmable, real-time hardware emulation tool for multiprocessor server design , 2000, SIGP.

[15]  Dong Liu,et al.  Modeling and evaluating heterogeneous memory architectures by trace-driven simulation , 2008, MAW '08.

[16]  Bruce McNutt.  The Fractal Structure of Data Reference: Applications to the Memory Hierarchy , 2000 .