论文信息 - Low-power implementation of polyphase filters in Quadratic Residue Number system

Low-power implementation of polyphase filters in Quadratic Residue Number system

The aim of this work is the reduction of the power dissipated in digital filters, while maintaining the timing unchanged. A polyphase filter bank in the Quadratic Residue Number System (QRNS) has been implemented and then compared, in terms of performance, area, and power dissipation to the implementation of a polyphase filter bank in the traditional two's complement system (TCS). The resulting implementations, designed to have the same clock rates, show that the QRNS filter is smaller and consumes less power than the TCS one.

[1] P. P. Vaidyanathan,et al. Filter banks in digital communications , 2001 .

[2] E. T.. An Introduction to the Theory of Numbers , 1946, Nature.

[3] Stephen A. Dyer,et al. Digital signal processing , 2018, 8th International Multitopic Conference, 2004. Proceedings of INMIC 2004..

[4] Michael A. Soderstrand,et al. Residue number system arithmetic: modern applications in digital signal processing , 1986 .

[5] Richard I. Tanaka,et al. Residue arithmetic and its applications to computer technology , 1967 .

[6] Gian Carlo Cardarilli,et al. Efficient Implementation of a Demultiplexer Based on a Multirate Filter Bank for the Skyplex Satellites DVB System , 2002, VLSI Design.

[7] Fred J. Taylor,et al. A Radix-4 FFT Using Complex RNS Arithmetic , 1985, IEEE Transactions on Computers.

[8] Thu V. Vu. Efficient Implementations of the Chinese Remainder Theorem for Sign Detection and Residue Decoding , 1985, IEEE Trans. Computers.

[9] Alexander Skavantzos,et al. On the binary quadratic residue system with noncoprime moduli , 1997, IEEE Trans. Signal Process..

[10] Gian Carlo Cardarilli,et al. RNS-to-binary conversion for efficient VLSI implementation , 1998 .

[11] S. Piestrak. A high-speed realization of a residue to binary number system converter , 1995 .