Bringing manufacturing into design via process-dependent SPICE models
暂无分享,去创建一个
Xiao Lin | L. Bomholt | Y. Mahotin | Dipu Pramanik | Victor Moroz | Lee Smith | S. Tirumala | S. Krishnamurthy | V. Moroz | D. Pramanik | Lee Smith | L. Bomholt | S. Tirumala | Xiao Lin | Y. Mahotin | S. Krishnamurthy
[1] Sani R. Nassif. Design for Variability in DSM Technologies , 2000 .
[2] James D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.
[3] Y. Mahotin,et al. Automatic BSIM3/4 Model Parameter Extraction with Penalty Function , 2004 .
[4] Sachin S. Sapatnekar,et al. Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal , 2003, ICCAD 2003.
[5] David Blaauw,et al. Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations , 2003, ICCAD 2003.
[6] Daniela De Venuto,et al. International Symposium on Quality Electronic Design , 2005, Microelectron. J..
[7] Kurt Keutzer,et al. A general probabilistic framework for worst case timing analysis , 2002, DAC '02.