High manufacturing-defect tolerance optically programmable architecture

Optically reconfigurable gate arrays, which consist simply of a holographic memory, a laser diode array, and a gate array VLSI, have a perfect parallel programmable capability. Even if a gate array VLSI includes defective areas, the perfect parallel programmable capability allows perfectly avoidance of those defective areas; instead, the remaining area on the gate array is used. Therefore, the architecture enables fabrication of large die VLSI chips and even wafer scale integrations using the latest processes with a high fraction of defects. Moreover, holographic memory is well-known to have high defect-tolerance because each bit of a reconfiguration context can be stored in the entire holographic memory and the damage of some component rarely affects its diffraction pattern or reconfiguration context. Therefore, the architecture has a high manufacturing-defect tolerance. In this paper, the high manufacturing-defect tolerance of optically programmable architectures is clarified using a single context prototype optically programmable architecture, which combines a liquid crystal spatial light modulator as a holographic memory, a He-Ne laser, and a perfectly parallel optically programmable gate-array VLSI.

[1]  Jose Mumbru,et al.  Optically programmable gate array , 2000, International Topical Meeting on Optics in Computing.

[2]  Minoru Watanabe,et al.  An optically differential reconfigurable gate array with a partial reconfiguration optical system and its power consumption estimation , 2004, 17th International Conference on VLSI Design. Proceedings..

[3]  Christopher Hess,et al.  Extraction of wafer-level defect density distributions to improve yield prediction , 1999, ICMTS 1999.

[4]  Jose Mumbru,et al.  Optical memory for computing and information processing , 1999, Optics + Photonics.

[5]  Anthony J. Yu,et al.  FPGA defect tolerance: impact of granularity , 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

[6]  Minoru Watanabe,et al.  An optically differential reconfigurable gate array and its power consumption estimation , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[7]  Minoru Watanabe,et al.  An optically differential reconfigurable gate array using a 0.18 /spl mu/m CMOS process , 2004, IEEE International SOC Conference, 2004. Proceedings..

[8]  Hideo Ito,et al.  Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey , 2003 .

[9]  Gan Zhou,et al.  Optically reconfigurable processors , 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).

[10]  C. Hess,et al.  Wafer level defect density distribution using checkerboard test structures , 1998, ICMTS 1998. Proceedings of 1998 International Conference on Microelectronic Test Structures (Cat. No.98CH36157).