Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip

This paper addresses the modeling and simulation of power supply voltage transients (Δ VDD) in digital SoC (Systems on a Chip), namely their impact on SoC core’s performance. The goal is to verify, in a cost-effective way, core’s fault tolerance to this disturbance, aiming at EMI/EMC standard compliance. The two key parameters are the time slack and the defect size. A top-down approach is used to introduce an innovative fault injection and simulation technique. In fact, fault simulation is carried out either by using faulty delays (defect size as a function of Δ VDD magnitude) in the CUT (Core Under Test) and nominal time excitation rate, or by using a fault-free CUT description and faster test application times (speed-up proportional to Δ VDD magnitude). A bottom-up approach, using electrical simulation, is extensively used to demonstrate the adequacy of exploiting this duality between time excitation and delay response, for combinational CUT. We refer this duality as the “accordion” effect. For sequential circuits, and for pipeline circuits, it is shown that the tolerance to Δ VDD disturbances is significantly lower than the one observed in combinational CUT, due to de-synchronization effects in storage elements. This effect depends on the clock distribution network and is a consequence of differently delayed responses of the CUT and of the clock network. Results are demonstrated using basic infrastructures and ISCAS benchmark circuits.