Highly Scalable NAND Flash Memory Cell Design Embracing Backside Charge Storage
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[1] J. Colinge. Silicon-on-Insulator Technology: Materials to VLSI , 1991 .
[2] Jungdal Choi,et al. Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure , 2008, 2008 Symposium on VLSI Technology.
[3] Choul-Young Kim,et al. Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology , 2015 .
[4] P.C.Y. Chen. Threshold-alterable Si-gate MOS devices , 1977, IEEE Transactions on Electron Devices.
[6] Dong Woo Kim,et al. Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory , 2006, 2009 Symposium on VLSI Technology.
[7] J. Bu,et al. On the go with SONOS , 2000 .
[8] Y. Iwata,et al. Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory , 2007, 2007 IEEE Symposium on VLSI Technology.
[9] Yoonjin Kim,et al. Efficient Fault-Recovery Technique for CGRA-based Multi-Core Architecture , 2015 .