A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-$Q$ Above-IC Inductors

A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input 1 dB compression point (IP-1dB ) is -9.5 dBm and the input referred third-order intercept point ( PIIP3 ) is + 2.25 dBm. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for RF ICs above 20 GHz.

[1]  Xiaoling Guo.  A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth , 2005 .

[2]  B. Heydari,et al.  30 GHz CMOS Low Noise Amplifier , 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

[4]  H. Jacobsson,et al.  A 15 GHz and a 20 GHz low noise amplifier in 90 nm RF-CMOS , 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[5]  Da-Chiang Chang,et al.  K-Band Low-Noise Amplifiers Using , 2004 .

[6]  P. Schvan,et al.  Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio , 2007, IEEE Journal of Solid-State Circuits.

[7]  Marc Tiebout,et al.  A 2kV ESD-Protected 18GHz LNA with 4dB NF in 0.13μm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[8]  Kyung-Wan Yu,et al.  K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology , 2004, IEEE Microwave and Wireless Components Letters.

[9]  K. O. Kenneth,et al.  An 800-μW 26-GHz CMOS tuned amplifier , 2006, RFIC 2006.

[10]  E. Beyne,et al.  Wafer-level packaging technology for high-Q on-chip inductors and transmission lines , 2004, IEEE Transactions on Microwave Theory and Techniques.

[11]  H. Jacobsson,et al.  A 20 GHz sub-1V low noise amplifier and a resistive mixer in 90 nm CMOS technology , 2005, 2005 Asia-Pacific Microwave Conference Proceedings.

[12]  K.-Y. Lin,et al.  A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 /spl mu/m CMOS technology , 2005, IEEE Microwave and Wireless Components Letters.

[13]  Piet Wambacq,et al.  A Mixed-Signal Design Roadmap , 2001, IEEE Des. Test Comput..