Towards approximation during test of Integrated Circuits

In the recent years, Approximate Computing (AC) has emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs). AC is based on the intuitive observation that, while performing exact computation requires a high amount of resources, allowing a selective approximation or an occasional relaxation of the specification can provide significant gains in energy efficiency. This work starts from the consideration that AC-based systems can intrinsically accept the presence of faulty hardware (i.e., hardware that can produce errors). In other words, an AC-based system does not need to be built using defect-free ICs. Under this assumption, we can relax test and reliability constraints of the manufactured ICs. One of the ways to achieve this goal is to test only for a subset of faults instead of targeting all possible faults. In this way, we can reduce the manufacturing cost since we reduce the number test patterns and thus the test time. We call this approach Approximate Test (AT). The main advantage is the fact that we do not need a prior knowledge of the application. Therefore, the proposed approach can be applied to any kind of IC, reducing the test time and increasing the yield. In this work, we aim at validating the proposed AT by comparing it with a functional approach. We present preliminary results on some simple case studies. The main goal is to show that by letting some faults undetected we can save test time without having a huge impact on the application quality.