Variation and failure characterization through pattern classification of test data from multiple test stages

We describe a framework for characterizing systematic variations and failures through exploring the hidden patterns of test data from multiple test stages. The framework provides prediction of process variations with a fine resolution based on a limited number of probed process parameters. An unsupervised biclustering technique is then utilized to extract grayscale and binary spatial patterns from process parameters and production test results, respectively, through analyzing both item-to-item and die-to-die correlations in subsets of the test data. A template matching technique exploits these spatial patterns to discover connections between process variations and failures detected by production tests. The proposed framework has been verified by an industrial test dataset of a non-volatile memory product. The discovery of comprehensible correlations between process parameters and some production test items was confirmed by the engineers who have insights to the test dataset.

[1]  Ulrich Bodenhofer,et al.  FABIA: factor analysis for bicluster acquisition , 2010, Bioinform..

[2]  Hong Wang,et al.  Joint Virtual Probe: Joint exploration of multiple test items' spatial patterns for efficient silicon characterization and test prediction , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[3]  Kenneth M. Butler,et al.  Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling , 2014, 2014 International Test Conference.

[4]  Kenneth M. Butler,et al.  Test cost reduction through performance prediction using virtual probe , 2011, 2011 IEEE International Test Conference.

[5]  Ming-Ju Wu,et al.  Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets , 2015, IEEE Transactions on Semiconductor Manufacturing.

[6]  Kenneth M. Butler,et al.  Test data analytics — Exploring spatial and test-item correlations in production test data , 2013, 2013 IEEE International Test Conference (ITC).

[7]  Arlindo L. Oliveira,et al.  Biclustering algorithms for biological data analysis: a survey , 2004, IEEE/ACM Transactions on Computational Biology and Bioinformatics.

[8]  Fei-Long Chen,et al.  A neural-network approach to recognize defect spatial pattern in semiconductor fabrication , 2000 .

[9]  Magdy S. Abadir,et al.  A pattern mining framework for inter-wafer abnormality analysis , 2013, 2013 IEEE International Test Conference (ITC).

[10]  Yiorgos Makris,et al.  Yield forecasting in fab-to-fab production migration based on Bayesian Model Fusion , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[11]  Yiorgos Makris,et al.  Process monitoring through wafer-level spatial variation decomposition , 2013, 2013 IEEE International Test Conference (ITC).

[12]  S. Nassif,et al.  Accurate Spatial Estimation and Decomposition Techniques for Variability Characterization , 2010, IEEE Transactions on Semiconductor Manufacturing.

[13]  Rob A. Rutenbar,et al.  Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[14]  Yiorgos Makris,et al.  Spatial estimation of wafer measurement parameters using Gaussian process models , 2012, 2012 IEEE International Test Conference.

[15]  Kwang-Ting Cheng,et al.  Learning from Production Test Data: Correlation Exploration and Feature Engineering , 2014, 2014 IEEE 23rd Asian Test Symposium.

[16]  J. P. Lewis Fast Normalized Cross-Correlation , 2010 .

[17]  Frank Liu,et al.  A General Framework for Spatial Correlation Modeling in VLSI Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[18]  Abhijit Chatterjee,et al.  Predicting die-level process variations from wafer test data for analog devices: A feasibility study , 2013, 2013 14th Latin American Test Workshop - LATW.

[19]  Paul D. Yoo,et al.  Machine-Learning-Based Identification of Defect Patterns in Semiconductor Wafer Maps: An Overview and Proposal , 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

[20]  Rob A. Rutenbar,et al.  Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Shang-Hong Lai,et al.  Fast Template Matching Based on Normalized Cross Correlation With Adaptive Multilevel Winner Update , 2008, IEEE Transactions on Image Processing.

[22]  Uwe D. Hanebeck,et al.  Template matching using fast normalized cross correlation , 2001, SPIE Defense + Commercial Sensing.

[23]  Suk Joo Bae,et al.  Detection of Spatial Defect Patterns Generated in Semiconductor Fabrication Processes , 2011, IEEE Transactions on Semiconductor Manufacturing.

[24]  Rob A. Rutenbar,et al.  Automatic clustering of wafer spatial signatures , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).