Evaluation of 3D interconnect routing and stacking strategy to optimize high speed signal transmission for memory on logic

3D stacking technologies are electrically studied to predict high speed data transmission for memory on logic applications. Maximal frequency of bandwidth for memory-processor and processor-BGA channels are extracted and compared for Face to Face and Face to Back 3D stacking and between an interposer technology. Using expected electrical specifications of Wide IO applications in terms of data rates, a roadmap is proposed in accordance to the integration density, carried out by the TSV density.

[1]  Junho Lee,et al.  I/O power estimation and analysis of high-speed channels in through-silicon via (TSV)-based 3D IC , 2010, 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems.

[2]  Young-Hyun Jun,et al.  A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking , 2011, 2011 IEEE International Solid-State Circuits Conference.

[3]  M. Facchini,et al.  Stackable memory of 3D chip integration for mobile applications , 2008, 2008 IEEE International Electron Devices Meeting.

[4]  Robert S. Patti.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs In 3D integrated circuits, analog, digital, flash and DRAM wafers are processed separately, then brought together in an integrated vertical stack. , 2006 .

[5]  Qawi Harvard,et al.  A scalable I/O architecture for wide I/O DRAM , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[6]  Jun-Seok Park,et al.  A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer , 2011, 2011 IEEE International Solid-State Circuits Conference.

[7]  Rao Tummala,et al.  Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[8]  Tomonori Sekiguchi,et al.  1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing , 2011, IEEE Journal of Solid-State Circuits.

[9]  John H. Lau,et al.  TSV manufacturing yield and hidden costs for 3D IC integration , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[10]  H. Reichl,et al.  3D integration of image sensor SiP using TSV silicon interposer , 2009, 2009 11th Electronics Packaging Technology Conference.

[11]  Dongwook Kim,et al.  Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV) , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[12]  B. Blampey,et al.  Presentation of a new time domain simulation tool and application to the analysis of advanced interconnect performance dependence on design and process parameters , 2004, Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects.

[13]  C. Ferrandon,et al.  Electrical characterization and impact on signal integrity of new basic interconnection elements inside 3D integrated circuits , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).