Thermal trends in emerging technologies

In the future, the peak temperature of a chip will be a primary design constraint. In order to meet this constraint, temperature must be considered in the earliest phases of the design process. Using a newly developed thermal analysis tool, HS3d, this work explores the thermal profile of devices as technology varies. We show that as technology scales, the hotspot locations can shift from the units with the most switching activity to those with the most low-threshold transistors. We further note that process variations in leakage dominated technologies can result in significant variations in the hotspot locations, indicating that feedback from thermal sensors will be very important. Finally, this work examines the thermal effects of multi-layer device stacking technologies, and finds that the vertical temperature difference between layers is much less significant than the horizontal differences due to power density, and as such, vertical placement optimizations will have much smaller impact on hotspot development than a uniform power distribution

[1]  Russell P. Kraft,et al.  3D direct vertical interconnect microprocessors test vehicle , 2003, GLSVLSI '03.

[2]  Chuan Seng Tan,et al.  Silicon Multilayer Stacking Based on Copper Wafer Bonding , 2005 .

[3]  Kaustav Banerjee,et al.  A new analytical thermal model for multilevel ULSI interconnects incorporating via effect , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[4]  J. Pineda de Gyvez,et al.  Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits , 2004, IEEE Journal of Solid-State Circuits.

[5]  M. Turowski,et al.  Fast, automated thermal simulation of three-dimensional integrated circuits , 2004, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).

[6]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[7]  Robert Patti,et al.  Techniques for Producing 3D ICs with High-Density Interconnect , 2004 .

[8]  M. Tomisaka,et al.  Thermal characterization of bare-die stacked modules with Cu through-vias , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[9]  Kevin Skadron,et al.  Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[10]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[11]  Krste Asanovic,et al.  Reducing power density through activity migration , 2003, ISLPED '03.

[12]  David Blaauw,et al.  Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, ISLPED '03.

[13]  Daniela De Venuto,et al.  International Symposium on Quality Electronic Design , 2005, Microelectron. J..

[14]  Bryan Black,et al.  3D processing technology and its impact on iA32 microprocessors , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[15]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[16]  Lawrence T. Pileggi,et al.  Efficient full-chip thermal modeling and analysis , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[17]  Margaret Martonosi,et al.  Dynamic thermal management for high-performance microprocessors , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[18]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).