Gain-Cell Embedded DRAMs: Modeling and Design Space

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as it relies on a storage cell that can be implemented with as few as two transistors and that can be fabricated without additional process steps. However, since the performance of GC-eDRAMs relies on many interdependent variables, the optimization of the performance of these memories for the integration into their hosting system, as well as the design investigation of future GC-eDRAMs, proves to be highly complex tasks. In this context, modeling tools of memories are key enablers for the exploration of this large design space in a short amount of time. In this article, we present GC-eDRAM modeling tool (GEMTOO), the first modeling tool that estimates timing, memory availability, bandwidth, and area of GC-eDRAMs. The tool considers parameters related to technology, circuits, and memory architecture, and it enables the evaluation of architectural transformations as well as advanced transistor-level effects, such as the increase in the access delay due to the deterioration of the stored data. The timing is estimated with a maximum deviation of 15% from postlayout simulations in a 28-nm FD-SOI technology for different memory sizes and architectures. Moreover, the measured random cycle frequency of a GC-eDRAM fabricated in a 28-nm CMOS bulk process is estimated with a 9% deviation when considering 6-sigma random process variations of the bitcells. The proposed GEMTOO modeling tool is used to show the intricacies in design optimization of GC-eDRAMs, and based on the results, optimal design practices are derived.

[1]  Norman P. Jouppi,et al.  CACTI: an enhanced cache access and cycle time model , 1996, IEEE J. Solid State Circuits.

[2]  Alexander Fish,et al.  Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling , 2013 .

[3]  Andreas Burg,et al.  GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Andreas Peter Burg,et al.  Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Ding-Ming Kwai,et al.  DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Alexander Fish,et al.  An 800-MHz Mixed- $V_{\text{T}}$ 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications , 2018, IEEE Journal of Solid-State Circuits.

[7]  Anantha P. Chandrakasan,et al.  A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices , 2017, IEEE Journal of Solid-State Circuits.

[8]  Jung Ho Ahn,et al.  A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies , 2008, 2008 International Symposium on Computer Architecture.

[9]  Andreas Peter Burg,et al.  Replica bit-line technique for embedded multilevel gain-cell DRAM , 2012, 10th IEEE International NEWCAS Conference.

[10]  Joel Emer,et al.  Eyeriss: an Energy-efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks Accessed Terms of Use , 2022 .

[11]  Norbert Wehn,et al.  DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool , 2015, International Journal of Parallel Programming.

[12]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[13]  Alexander Fish,et al.  A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Thomas A. DeMassa,et al.  Digital Integrated Circuits , 1985, 1985 IEEE GaAs IC Symposium Technical Digest.

[15]  Andreas Peter Burg,et al.  An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications , 2017, ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference.

[16]  Yibin Ye,et al.  2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology , 2009, IEEE Journal of Solid-State Circuits.

[17]  Thomas Vogelsang,et al.  Understanding the Energy Consumption of Dynamic Random Access Memories , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[18]  Chris H. Kim,et al.  A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches , 2011, IEEE Journal of Solid-State Circuits.

[19]  Alexander Fish,et al.  Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip , 2017 .

[20]  David Blaauw,et al.  A 5.42nW/kB retention power logic-compatible embedded DRAM with 2T dual-Vt gain cell for low power sensing applications , 2010, 2010 IEEE Asian Solid-State Circuits Conference.

[21]  Y. Itoh,et al.  0.5 V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[22]  Luca Benini,et al.  Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.