Logic and Architecture Synthesis
暂无分享,去创建一个
[1] Peter Duzy,et al. High-level synthesis from VHDL with exact timing constraints , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[2] Hugo De Man,et al. Instruction set definition and instruction selection for ASIPs , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.
[3] Wolfgang Rosenstiel,et al. Scheduling and Assignment in High Level Synthesis , 1991 .
[4] Howard Trickey,et al. Flamel: A High-Level Hardware Compiler , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Hans Eveking,et al. Optimization and Resynthesis of Complex Data-Paths , 1993, 30th ACM/IEEE Design Automation Conference.
[6] Zafar Hasan,et al. On Multi-Cycle False Paths in Sequential Circuits , 1995 .
[7] Pascal Raymond,et al. The synchronous data flow programming language LUSTRE , 1991, Proc. IEEE.
[8] Gabriele Saucier,et al. State assignment of controllers for optimal area implementation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[9] I. Karkowski,et al. Circuit delay optimization as a multiple choice linear knapsack program , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[10] Fadi J. Kurdahi,et al. REAL: A Program for REgister ALlocation , 1987, 24th ACM/IEEE Design Automation Conference.
[11] Bernard Courtois,et al. CAD and testing of ICs and systems: where are we going? , 1994 .
[12] Régis Leveugle,et al. Analysis and comparison of fault tolerant FSM architecture based on SEC codes , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.
[13] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[14] Steve Golson. One-hot state machine design for FPGAs , 1993 .
[15] B. Zavidovique,et al. A complete environment for global architecture synthesis , 1993, 1993 Computer Architectures for Machine Perception.
[16] Charles E. Leiserson,et al. Optimizing Synchronous Circuitry by Retiming (Preliminary Version) , 1983 .
[17] Giovanni De Micheli,et al. High Level Synthesis of ASlCs un - der Timing and Synchronization Constraints , 1992 .
[18] Alice C. Parker,et al. Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[19] Andreas Münzner,et al. Converting combinational circuits into pipelined data paths , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[20] Barry M. Pangrle,et al. Conditional and unconditional hardware sharing in pipeline synthesis , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.
[21] Peter Marwedel,et al. Tree-based mapping of algorithms to predefined structures , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[22] B. Ramesh,et al. Low sensitivity digital LDI ladder filters with elliptic magnitude response , 1986 .
[23] Hugo De Man,et al. High-level synthesis for real-time digital signal processing , 1993, The Kluwer international series in engineering and computer science.
[24] Olivier Sentieys,et al. GAUT: An architectural synthesis tool for dedicated signal processors , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.
[25] D.D. Gajski,et al. An Expert-System Paradigm for Design , 1986, 23rd ACM/IEEE Design Automation Conference.
[26] Peter B. Denyer,et al. A new approach to pipeline optimisation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[27] Alain J. Martin. Asynchronous datapaths and the design of an asynchronous adder , 1992, Formal Methods Syst. Des..
[28] Wolfgang Rosenstiel,et al. Interface specification and synthesis for VHDL processes , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.
[29] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.
[30] Gabriele Saucier,et al. Specification and Synthesis of Communicating Finite State Machines , 1992, Synthesis for Control Dominated Circuits.
[31] Jean-Michel Muller,et al. The CORDIC Algorithm: New Results for Fast VLSI Implementation , 1993, IEEE Trans. Computers.
[32] Jack Sklansky,et al. Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..
[33] Peter Duzy,et al. The Synthesis Approach to Digital System Design , 1992 .
[34] Pietro Andreani,et al. Custom DSP implementation of a GSM speech coder , 1993 .
[35] David C. Hendry,et al. DSP datapath synthesis eliminating global interconnect , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.
[36] Ing-Jer Huang,et al. Synthesis of application specific instruction sets , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[37] Minjoong Rim,et al. Representing conditional branches for high-level synthesis applications , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[38] H. Veit,et al. CASTLE: an interactive environment for HW-SW co-design , 1994, Third International Workshop on Hardware/Software Codesign.
[39] Wolfgang Rosenstiel,et al. System synthesis using behavioural descriptions , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[40] Jan M. Rabaey,et al. Power estimation for high level synthesis , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[41] Giovanni De Micheli,et al. Hardware-software cosynthesis for digital systems , 1993, IEEE Design & Test of Computers.
[42] Thomas Lengauer,et al. Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.
[43] Régis Leveugle. Optimized State Assignment of Single Fault Tolerant FSMs Based on SEC Codes , 1993, 30th ACM/IEEE Design Automation Conference.
[44] Guido Henri Marguerite Petit,et al. Vlsi architecture of a smds/atm router , 1993 .
[45] Hans-Georg Martin. Retiming by combination of relocation and clock delay adjustment , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.
[46] Jean Vuillemin,et al. Introduction to programmable active memories , 1990 .
[47] Arno Kunzmann,et al. Generation of deterministic test patterns by minimal basic test sets , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[48] Raul Camposano,et al. Path-based scheduling for synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[49] Kazutoshi Wakabayashi,et al. Global scheduling independent of control dependencies based on condition vectors , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[50] J.T.J. van Eijndhoven,et al. A data flow graph exchange standard , 1992, [1992] Proceedings The European Conference on Design Automation.
[51] Alice C. Parker,et al. Tutorial on high-level synthesis , 1988, DAC '88.
[52] Gert Goossens,et al. Code Generation for Embedded Processors , 1995 .
[53] Hans-Joachim Wunderlich,et al. Tools and devices supporting the pseudo-exhaustive test , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..
[54] A. Richard Newton,et al. Has CAD for VLSI Reached a Dead End? , 1991, VLSI.
[55] Christian Ewering,et al. Automatic high level synthesis of partitioned busses , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[56] Michael H. Schulz,et al. Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[57] Raul Camposano,et al. Design of an embedded video compression system-a quantitative approach , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[58] Donald E. Thomas,et al. The combination of scheduling, allocation, and mapping in a single algorithm , 1991, DAC '90.
[59] Masahiko Yoshimoto,et al. A 100-MHz 2-D discrete cosine transform core processor , 1992 .
[60] F. Brglez,et al. McMAP: a fast technology mapping procedure for multi-level logic synthesis , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[61] Wolfgang Rosenstiel,et al. Automatic module allocation in high level synthesis , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[62] Daniel D. Gajski,et al. High ― Level Synthesis: Introduction to Chip and System Design , 1992 .
[63] Hugo De Man,et al. Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms , 1990, Proc. IEEE.
[64] Christian Berthet,et al. Synthesis of VHDL arrays on RAM cells , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[65] G.M. Quenot,et al. A reconfigurable compute engine for real-time vision automata prototyping , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.
[66] Fadi J. Kurdahi,et al. Combined topological and functionality based delay estimation using a layout-driven approach for high level applications , 1994, EURO-DAC '92.
[67] Kazutoshi Wakabayashi,et al. A resource sharing and control synthesis method for conditional branches , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[68] Mark Hirsch,et al. Automatically extracting structure from a logical design , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[69] Arno Kunzmann,et al. An analytical approach to the partial scan problem , 1990, J. Electron. Test..
[70] Jörg Biesenack,et al. The Siemens high-level synthesis system CALLAS , 1993, IEEE Trans. Very Large Scale Integr. Syst..
[71] Kishor S. Trivedi,et al. On-line algorithms for division and multiplication , 1975, 1975 IEEE 3rd Symposium on Computer Arithmetic (ARITH).
[72] A. H. Timmer,et al. Module selection and scheduling using unrestricted libraries , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[73] Olivier Sentieys,et al. VLSI architectural synthesis for an acoustic echo cancellation application , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.
[74] D.D. Gajski,et al. An algorithm for component selection in performance optimized scheduling , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[75] Jonathan Rose,et al. The effect of logic block architecture on FPGA performance , 1992 .
[76] Henk Corporaal,et al. Transport-Triggering versus Operation-Triggering , 1994, CC.
[77] Heinrich Theodor Vierhaus,et al. System-Synthesis using Hardware/Software Codesign , 1993 .
[78] Wayne H. Wolf,et al. The Princeton University behavioral synthesis system , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[79] Marius Strum,et al. Pseudoexhaustive test techniques: a new algorithm to partition combinational networks , 1989, [1989] Proceedings of the 1st European Test Conference.
[80] A. Alomary,et al. PEAS-I: A hardware/software co-design system for ASIPs , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.
[81] R. Bryant. Graph-Based Algorithms for Boolean Function Manipulation12 , 1986 .
[82] Srinivas Devadas,et al. Algorithms for hardware allocation in data path synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[83] G. Goossens,et al. Architectural synthesis for medium and high throughput signal processing with the new Cathedral environment , 1991 .
[84] Gotaro Odawara,et al. Partitioning and Placement Technique for CMOS Gate Arrays , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[85] T. C. May,et al. Instruction-set matching and selection for DSP and ASIP code generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[86] Robert K. Brayton,et al. Retiming and Resynthesis: Optimizing Sequential Networks with , 1990 .
[87] Régis Leveugle,et al. Generation of optimized datapaths: bit-slice versus standard cells , 1992, Synthesis for Control Dominated Circuits.
[88] E. Rechtin,et al. The art of systems architecting , 1996, IEEE Spectrum.
[89] Giovanni De Micheli,et al. Synthesis and Optimization of Digital Circuits , 1994 .
[90] Robert A. Walker,et al. A Survey of high-level synthesis systems , 1991 .
[91] Norbert Wehn,et al. Scheduling of behavioral VHDL by retiming techniques , 1994, EURO-DAC '94.
[92] S. Whitaker,et al. Fault tolerant sequential circuits using sequence invariant state machines , 1991 .
[93] Fadi J. Kurdahi,et al. LAST: a layout area and shape function estimator for high level applications , 1991, Proceedings of the European Conference on Design Automation..
[94] Hans-Joachim Wunderlich,et al. Generating pseudo-exhaustive vectors for external testing , 1990, Proceedings. International Test Conference 1990.
[95] F.J. Kurdahi,et al. TELE: a timing evaluator using layout estimation for high level applications , 1992, [1992] Proceedings The European Conference on Design Automation.
[96] Fadi J. Kurdahi,et al. The effects of variations in component styles and shapes on high-level synthesis , 1992 .