EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism

The paper presents a new channel allocation method for higher Embedded Deterministic Test (EDT) compression in SoC designs comprising isolated cores. It employs a test data reduction technique, which allows cores to interface with ATE through an optimized number of channels. This feature is subsequently used by a new test scheduling and test access mechanisms devised for both the input and output sides. Experimental results obtained for large industrial SoC designs illustrate feasibility of the proposed test application scheme and are reported herein.

[1]  Hideo Fujiwara,et al.  System-on-chip test scheduling with reconfigurable core wrappers , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Julien Pouget,et al.  Defect-aware SOC test scheduling , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[3]  Nicola Nicolici,et al.  Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels , 2005, European Test Symposium (ETS'05).

[4]  Nur A. Touba,et al.  Testing embedded cores using partial isolation rings , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[5]  Petru Eles,et al.  A heuristic for thermal-safe SoC test scheduling , 2007, 2007 IEEE International Test Conference.

[6]  Qiang Xu,et al.  Multi-frequency test access mechanism design for modular SOC testing , 2004, 13th Asian Test Symposium.

[7]  Irith Pomeranz,et al.  SOC test scheduling using simulated annealing , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[8]  Nur A. Touba,et al.  Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[9]  Vishwani D. Agrawal,et al.  Scheduling tests for VLSI systems under power constraints , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Kedarnath J. Balakrishnan,et al.  Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[11]  Erik Jan Marinissen,et al.  IEEE P1500-compliant test wrapper design for hierarchical cores , 2004 .

[12]  Qiang Xu,et al.  Time/area tradeoffs in testing hierarchical SOCs with hard mega-cores , 2004, 2004 International Conferce on Test.

[13]  Erik G. Larsson,et al.  An Integrated Framework for the Design and Optimization of SOC Test Solutions , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[14]  Krishnendu Chakrabarty,et al.  A unified approach to reduce SOC test data volume, scan power and testing time , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Krishnendu Chakrabarty,et al.  Accepted for Publication in Ieee Transactions on Computer-aided Design of Integrated Circuits and Systems Test Scheduling for Core-based Systems Using Mixed-integer Linear Programming , 2000 .

[16]  Nilanjan Mukherjee,et al.  Dynamic channel allocation for higher EDT compression in SoC designs , 2010, 2010 IEEE International Test Conference.

[17]  Erik Jan Marinissen,et al.  Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip , 2002, J. Electron. Test..

[18]  Erik Jan Marinissen,et al.  Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip , 2003, IEEE Trans. Computers.

[19]  Petru Eles,et al.  Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving , 2008, J. Electron. Test..

[20]  Erik Jan Marinissen,et al.  Test scheduling for modular SOCs in an abort-on-fail environment , 2005, European Test Symposium (ETS'05).

[21]  Erik Jan Marinissen,et al.  Effective and efficient test architecture design for SOCs , 2002, Proceedings. International Test Conference.

[22]  Erik G. Larsson,et al.  Power constrained preemptive TAM scheduling , 2002, Proceedings The Seventh IEEE European Test Workshop.

[23]  Wu-Tung Cheng,et al.  X-filter: filtering unknowns from compacted test responses , 2005, IEEE International Conference on Test, 2005..

[24]  Erik Jan Marinissen,et al.  Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[25]  Bashir M. Al-Hashimi,et al.  A compression-driven test access mechanism design approach , 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

[26]  Shambhu J. Upadhyaya,et al.  Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  M. Chrzanowska-Jeske,et al.  Using a distributed rectangle bin-packing approach for core-based SoC test scheduling with power constraints , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[28]  Parameswaran Ramanathan,et al.  Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies , 2009, 2009 Asian Test Symposium.

[29]  Krishnendu Chakrabarty,et al.  Test planning for modular testing of hierarchical SOCs , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Krishnendu Chakrabarty,et al.  System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Erik Jan Marinissen,et al.  Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling , 2009, IEEE Transactions on Computers.

[32]  Alexandre M. Amory,et al.  Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism , 2006, Eleventh IEEE European Test Symposium (ETS'06).

[33]  Spyros Tragoudas,et al.  Interconnect testing for networks on chips , 2006, 24th IEEE VLSI Test Symposium.

[34]  Srivaths Ravi,et al.  A generic low power scan chain wrapper for designs using scan compression , 2010, 2010 28th VLSI Test Symposium (VTS).

[35]  Erik Jan Marinissen,et al.  Efficient test access mechanism optimization for system-on-chip , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[36]  Krishnendu Chakrabarty,et al.  SOC test planning using virtual test access architectures , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[37]  Krishnendu Chakrabarty.  A synthesis-for-transparency approach for hierarchical and system-on-a-chip test , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[38]  Richard M. Karp,et al.  A n^5/2 Algorithm for Maximum Matchings in Bipartite Graphs , 1971, SWAT.

[39]  Krishnendu Chakrabarty,et al.  A unified approach for SoC testing using test data compression and TAM optimization , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[40]  Yervant Zorian,et al.  Wrapper design for embedded core test , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[41]  Krishnendu Chakrabarty,et al.  Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[42]  Jing Wang,et al.  Test access mechanism for multiple identical cores , 2008, 2009 International Test Conference.

[43]  Nilanjan Mukherjee,et al.  Embedded deterministic test , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[44]  Krishnendu Chakrabarty,et al.  Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[45]  Sujit Dey,et al.  A fast and low cost testing technique for core-based system-on-chip , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[46]  Dhiraj K. Pradhan,et al.  Thermal-aware testing of network-on-chip using multiple-frequency clocking , 2006, 24th IEEE VLSI Test Symposium.

[47]  Nilanjan Mukherjee,et al.  Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm , 2002, Proceedings. International Test Conference.

[48]  Dhiraj K. Pradhan,et al.  Test scheduling for network-on-chip with BIST and precedence constraints , 2004, 2004 International Conferce on Test.

[49]  Sandeep Koranne.  Formulation of SOC Test Scheduling as a Network Transportation Problem , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[50]  Mark Mohammad Tehranipoor,et al.  Nine-coded compression technique for testing embedded cores in SoCs , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[51]  Nilanjan Mukherjee,et al.  X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.