Delay locked loop circuit for correcting duty cycle of clock signal and delay locking method

PURPOSE: A delay locked loop and a delay locked method correcting a duty cycle of a clock signal are provided, which generate an internal clock signal with a low jitter, and generate a jitter included in the internal clock signal. CONSTITUTION: A delay locked loop circuit(321) comprises the first delay locked loop circuit(331), the second delay locked loop circuit(332), a waveform mixer(351), a compensation delay(341) and inverters(361,362). A duty cycle corrector(311) generates an output signal(Clk_dcc) by correcting a duty cycle of an external clock signal(Clk_ext). The delay locked loop circuit inputs the external clock signal and the output signal of the duty cycle corrector and a feedback clock signal(Clk_fd) and generates an internal clock signal. The first and the second delay locked loop circuit are connected in parallel each other, and the duty cycle of the external clock signal is corrected by the first and the second delay locked loop circuit. The first delay locked loop circuit inputs the external clock signal and the output signal of the duty cycle corrector and the feedback clock signal and generates the first clock signal(Clk_r). The compensation delay generates a feedback clock signal by delaying the internal clock signal, and the inverters output signals(Clk_dccb,Clk_fbb) by inverting the output signal of the duty cycle corrector and the feedback clock signal. The second delay locked loop circuit generates the second clock signal(Clk_f). And the waveform mixer inputs the first and the second clock signal and generates an internal clock signal(Clk_int).