Thermally-Aware Layout Design of β-Ga₂O₃ Lateral MOSFETs

<inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-phase gallium oxide (<inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-Ga₂O₃) is drawing significant attention in the power electronics field due to its remarkable critical electric field strength [greater than gallium nitride (GaN) and silicon carbide (SiC)] and the availability of high-quality melt-grown substrates providing the opportunity for low-cost manufacturing. However, because of the low thermal conductivity of <inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-Ga₂O₃, thermal management strategies at the device-level are required to achieve the targeted high-power capabilities. In this work, the effects of the anisotropic thermal conductivity of <inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-Ga₂O₃ and the geometrical design of the metal electrodes/interconnects on the device self-heating were investigated. For a power density (<inline-formula> <tex-math notation="LaTeX">${P}_{\text {dis}}$ </tex-math></inline-formula>) of 1 W/mm at <inline-formula> <tex-math notation="LaTeX">${V}_{\text {GS}} =$ </tex-math></inline-formula> 4 V (i.e., a fully open channel condition), when the channel width is along a direction perpendicular to (<inline-formula> <tex-math notation="LaTeX">$\bar {{2}}{01}$ </tex-math></inline-formula>), the channel temperature decreases by 10% as compared to a case aligning the channel length along the direction close to [100]. Also, by decreasing the width of the interconnect between the drain electrode and the metal bond pad (serving as a heat pathway) from 100 to <inline-formula> <tex-math notation="LaTeX">$10~\mu \text{m}$ </tex-math></inline-formula> (90% reduction), the channel temperature increased by ~8% for <inline-formula> <tex-math notation="LaTeX">${P}_{\text {dis}} =$ </tex-math></inline-formula> 1 W/mm. Last, for devices with identical heat generation profiles, increasing the distance between the gate and drain contact from 1 to 10 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>, results in a 35% increase in the channel temperature rise. This work highlights the importance of thermally aware device layout design for lateral <inline-formula> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula>-Ga₂O₃ transistors, in terms of maximizing both the electrical and thermal performance.